The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article présente un simulateur précis au cycle pour un système multimédia reconfigurable dynamiquement, appelé SimREMUS. SimREMUS peut être utilisé soit au niveau des transactions, ce qui permet la modélisation et la simulation de matériel de niveau supérieur et de logiciels embarqués, soit au niveau du transfert de registre, si l'on souhaite observer le comportement dynamique du système au niveau du signal. Les compromis entre un ensemble de critères fréquemment utilisés pour caractériser la conception d'un système informatique reconfigurable, tels que la granularité, la programmabilité, la configurabilité ainsi que l'architecture des éléments de traitement et des modules de routage, etc., peuvent être rapidement évalués. De plus, une chaîne d'outils complète pour SimREMUS, comprenant un compilateur et un débogueur, est développée. SimREMUS pourrait simuler 270 264 cycles par seconde pour un SoC (System-on-a-Chip) à un million de portes et produire une image H.1080 15p en 5200 minutes, ce qui pourrait coûter des jours sur VCS (plate-forme : CPU : E2.5@ 2.0 Ghz, RAM : 1080 Go). La simulation a montré que 30p à 264 ips de H.4 High Profile @ niveau 200 peuvent être obtenus en exploitant une fréquence de travail de XNUMX MHz sur l'architecture VLSI de REMUS.
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Min ZHU, Leibo LIU, Shouyi YIN, Chongyong YIN, Shaojun WEI, "A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 12, pp. 3202-3210, December 2010, doi: 10.1587/transinf.E93.D.3202.
Abstract: This paper introduces a cycle-accurate Simulator for a dynamically REconfigurable MUlti-media System, called SimREMUS. SimREMUS can either be used at transaction-level, which allows the modeling and simulation of higher-level hardware and embedded software, or at register transfer level, if the dynamic system behavior is desired to be observed at signal level. Trade-offs among a set of criteria that are frequently used to characterize the design of a reconfigurable computing system, such as granularity, programmability, configurability as well as architecture of processing elements and route modules etc., can be quickly evaluated. Moreover, a complete tool chain for SimREMUS, including compiler and debugger, is developed. SimREMUS could simulate 270 k cycles per second for million gates SoC (System-on-a-Chip) and produced one H.264 1080p frame in 15 minutes, which might cost days on VCS (platform: CPU: E5200@ 2.5 Ghz, RAM: 2.0 GB). Simulation showed that 1080p@30 fps of H.264 High Profile@ Level 4 can be achieved when exploiting a 200 MHz working frequency on the VLSI architecture of REMUS.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.3202/_p
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@ARTICLE{e93-d_12_3202,
author={Min ZHU, Leibo LIU, Shouyi YIN, Chongyong YIN, Shaojun WEI, },
journal={IEICE TRANSACTIONS on Information},
title={A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System},
year={2010},
volume={E93-D},
number={12},
pages={3202-3210},
abstract={This paper introduces a cycle-accurate Simulator for a dynamically REconfigurable MUlti-media System, called SimREMUS. SimREMUS can either be used at transaction-level, which allows the modeling and simulation of higher-level hardware and embedded software, or at register transfer level, if the dynamic system behavior is desired to be observed at signal level. Trade-offs among a set of criteria that are frequently used to characterize the design of a reconfigurable computing system, such as granularity, programmability, configurability as well as architecture of processing elements and route modules etc., can be quickly evaluated. Moreover, a complete tool chain for SimREMUS, including compiler and debugger, is developed. SimREMUS could simulate 270 k cycles per second for million gates SoC (System-on-a-Chip) and produced one H.264 1080p frame in 15 minutes, which might cost days on VCS (platform: CPU: E5200@ 2.5 Ghz, RAM: 2.0 GB). Simulation showed that 1080p@30 fps of H.264 High Profile@ Level 4 can be achieved when exploiting a 200 MHz working frequency on the VLSI architecture of REMUS.},
keywords={},
doi={10.1587/transinf.E93.D.3202},
ISSN={1745-1361},
month={December},}
Copier
TY - JOUR
TI - A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System
T2 - IEICE TRANSACTIONS on Information
SP - 3202
EP - 3210
AU - Min ZHU
AU - Leibo LIU
AU - Shouyi YIN
AU - Chongyong YIN
AU - Shaojun WEI
PY - 2010
DO - 10.1587/transinf.E93.D.3202
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2010
AB - This paper introduces a cycle-accurate Simulator for a dynamically REconfigurable MUlti-media System, called SimREMUS. SimREMUS can either be used at transaction-level, which allows the modeling and simulation of higher-level hardware and embedded software, or at register transfer level, if the dynamic system behavior is desired to be observed at signal level. Trade-offs among a set of criteria that are frequently used to characterize the design of a reconfigurable computing system, such as granularity, programmability, configurability as well as architecture of processing elements and route modules etc., can be quickly evaluated. Moreover, a complete tool chain for SimREMUS, including compiler and debugger, is developed. SimREMUS could simulate 270 k cycles per second for million gates SoC (System-on-a-Chip) and produced one H.264 1080p frame in 15 minutes, which might cost days on VCS (platform: CPU: E5200@ 2.5 Ghz, RAM: 2.0 GB). Simulation showed that 1080p@30 fps of H.264 High Profile@ Level 4 can be achieved when exploiting a 200 MHz working frequency on the VLSI architecture of REMUS.
ER -