The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Nous exploitons un schéma de représentation structurelle des connaissances appelé méthodologie System Entity Structure (SES) pour représenter et gérer les modèles de défaillance des plaquettes qui peuvent avoir une influence significative sur les FAB dans l'industrie des semi-conducteurs. Il est important que les ingénieurs simulent divers processus de vérification du système en utilisant des entités système prédéfinies (par exemple, décomposition, taxonomie et relations de couplage d'un système) contenues dans le SES. Pour de meilleures performances de calcul, compte tenu d'un certain modèle de défaillance, un SES élagué (PES) peut être extrait en sélectionnant les seules entités système pertinentes du SES. Par conséquent, le système de simulation basé sur SES permet aux ingénieurs d'évaluer et de surveiller efficacement les données sur les semi-conducteurs en i) analyser les échecs pour découvrir les causes correspondantes et ii) gérer les données historiques liées à de telles pannes.
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Young-Shin HAN, SoYoung KIM, TaeKyu KIM, Jason J. JUNG, "Automatic Defect Classification System in Semiconductors EDS Test Based on System Entity Structure Methodology" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 7, pp. 2001-2004, July 2010, doi: 10.1587/transinf.E93.D.2001.
Abstract: We exploit a structural knowledge representation scheme called System Entity Structure (SES) methodology to represent and manage wafer failure patterns which can make a significant influence to FABs in the semiconductor industry. It is important for the engineers to simulate various system verification processes by using predefined system entities (e.g., decomposition, taxonomy, and coupling relationships of a system) contained in the SES. For better computational performance, given a certain failure pattern, a Pruned SES (PES) can be extracted by selecting the only relevant system entities from the SES. Therefore, the SES-based simulation system allows the engineers to efficiently evaluate and monitor semiconductor data by i) analyzing failures to find out the corresponding causes and ii) managing historical data related to such failures.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.2001/_p
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@ARTICLE{e93-d_7_2001,
author={Young-Shin HAN, SoYoung KIM, TaeKyu KIM, Jason J. JUNG, },
journal={IEICE TRANSACTIONS on Information},
title={Automatic Defect Classification System in Semiconductors EDS Test Based on System Entity Structure Methodology},
year={2010},
volume={E93-D},
number={7},
pages={2001-2004},
abstract={We exploit a structural knowledge representation scheme called System Entity Structure (SES) methodology to represent and manage wafer failure patterns which can make a significant influence to FABs in the semiconductor industry. It is important for the engineers to simulate various system verification processes by using predefined system entities (e.g., decomposition, taxonomy, and coupling relationships of a system) contained in the SES. For better computational performance, given a certain failure pattern, a Pruned SES (PES) can be extracted by selecting the only relevant system entities from the SES. Therefore, the SES-based simulation system allows the engineers to efficiently evaluate and monitor semiconductor data by i) analyzing failures to find out the corresponding causes and ii) managing historical data related to such failures.},
keywords={},
doi={10.1587/transinf.E93.D.2001},
ISSN={1745-1361},
month={July},}
Copier
TY - JOUR
TI - Automatic Defect Classification System in Semiconductors EDS Test Based on System Entity Structure Methodology
T2 - IEICE TRANSACTIONS on Information
SP - 2001
EP - 2004
AU - Young-Shin HAN
AU - SoYoung KIM
AU - TaeKyu KIM
AU - Jason J. JUNG
PY - 2010
DO - 10.1587/transinf.E93.D.2001
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 2010
AB - We exploit a structural knowledge representation scheme called System Entity Structure (SES) methodology to represent and manage wafer failure patterns which can make a significant influence to FABs in the semiconductor industry. It is important for the engineers to simulate various system verification processes by using predefined system entities (e.g., decomposition, taxonomy, and coupling relationships of a system) contained in the SES. For better computational performance, given a certain failure pattern, a Pruned SES (PES) can be extracted by selecting the only relevant system entities from the SES. Therefore, the SES-based simulation system allows the engineers to efficiently evaluate and monitor semiconductor data by i) analyzing failures to find out the corresponding causes and ii) managing historical data related to such failures.
ER -