The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Les tests d'analyse à grande vitesse sont susceptibles de présenter un risque de perte de rendement en raison du bruit de l'alimentation électrique provoqué par une activité excessive de commutation de lancement. Cet article propose un nouveau schéma en deux étapes, à savoir CTX (Clock-Gating-Based Test Relaxation and X-Filling), pour réduire l'activité de commutation lorsqu'un stimulus de test est lancé. Des tests de relaxation et de remplissage X sont effectués (1) pour rendre inactifs autant de FF que possible en désactivant les signaux de commande d'horloge correspondants des circuits de déclenchement d'horloge à l'étape 1 (désactivation de l'horloge), et (2) pour égaliser l'entrée et la sortie. valeurs à l’étape 2 d’autant de FF actifs restants que possible (FF-Silencing). CTX réduit efficacement l'activité de commutation de lancement et donc le risque de perte de rendement même lorsque seul un petit nombre de bits indifférents (X) sont présents (comme dans la compression de test) sans aucun impact sur le volume des données de test, la couverture des défauts, les performances ou la conception du circuit. .
Kohei MIYASE
Xiaoqing WEN
Hiroshi FURUKAWA
Yuta YAMATO
Seiji KAJIHARA
Patrick GIRARD
Laung-Terng WANG
Mohammad TEHRANIPOOR
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Kohei MIYASE, Xiaoqing WEN, Hiroshi FURUKAWA, Yuta YAMATO, Seiji KAJIHARA, Patrick GIRARD, Laung-Terng WANG, Mohammad TEHRANIPOOR, "High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 1, pp. 2-9, January 2010, doi: 10.1587/transinf.E93.D.2.
Abstract: At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when a test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs as possible inactive by disabling corresponding clock control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to equalize the input and output values in Stage-2 of as many remaining active FFs as possible (FF-Silencing). CTX effectively reduces launch switching activity and thus yield loss risk even when only a small number of don't care (X) bits are present (as in test compression) without any impact on test data volume, fault coverage, performance, or circuit design.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.2/_p
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@ARTICLE{e93-d_1_2,
author={Kohei MIYASE, Xiaoqing WEN, Hiroshi FURUKAWA, Yuta YAMATO, Seiji KAJIHARA, Patrick GIRARD, Laung-Terng WANG, Mohammad TEHRANIPOOR, },
journal={IEICE TRANSACTIONS on Information},
title={High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme},
year={2010},
volume={E93-D},
number={1},
pages={2-9},
abstract={At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when a test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs as possible inactive by disabling corresponding clock control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to equalize the input and output values in Stage-2 of as many remaining active FFs as possible (FF-Silencing). CTX effectively reduces launch switching activity and thus yield loss risk even when only a small number of don't care (X) bits are present (as in test compression) without any impact on test data volume, fault coverage, performance, or circuit design.},
keywords={},
doi={10.1587/transinf.E93.D.2},
ISSN={1745-1361},
month={January},}
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TY - JOUR
TI - High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme
T2 - IEICE TRANSACTIONS on Information
SP - 2
EP - 9
AU - Kohei MIYASE
AU - Xiaoqing WEN
AU - Hiroshi FURUKAWA
AU - Yuta YAMATO
AU - Seiji KAJIHARA
AU - Patrick GIRARD
AU - Laung-Terng WANG
AU - Mohammad TEHRANIPOOR
PY - 2010
DO - 10.1587/transinf.E93.D.2
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 1
JA - IEICE TRANSACTIONS on Information
Y1 - January 2010
AB - At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when a test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs as possible inactive by disabling corresponding clock control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to equalize the input and output values in Stage-2 of as many remaining active FFs as possible (FF-Silencing). CTX effectively reduces launch switching activity and thus yield loss risk even when only a small number of don't care (X) bits are present (as in test compression) without any impact on test data volume, fault coverage, performance, or circuit design.
ER -