The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article présente une conception de balayage pour la testabilité des défauts de retard des circuits logiques à 2 rails. Les bascules utilisées dans la conception du scan sont basées sur celles maître-esclave. La conception de balayage proposée offre une couverture complète des défauts lors des tests de défauts de retard des circuits logiques à 2 rails. Dans les tests à deux modèles avec la conception de balayage proposée, les vecteurs initiaux sont définis à l'aide de l'opération de définition-réinitialisation, et l'opération de numérisation pour les vecteurs initiaux n'est pas requise. Par conséquent, le temps d’application du test est réduit d’environ la moitié de celui de la conception d’analyse améliorée. Etant donné que la fonction supplémentaire est uniquement l'opération de réinitialisation du verrou esclave, la surcharge de zone est faible. L'évaluation montre que les différences dans la zone de surcharge de la conception d'analyse proposée par rapport à celles de la conception d'analyse standard et de la conception d'analyse améliorée sont de 2.1 et -14.5 pour cent en moyenne, respectivement.
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Kentaroh KATOH, Kazuteru NAMBA, Hideo ITO, "Design for Delay Fault Testability of 2-Rail Logic Circuits" in IEICE TRANSACTIONS on Information,
vol. E92-D, no. 2, pp. 336-341, February 2009, doi: 10.1587/transinf.E92.D.336.
Abstract: This paper presents a scan design for delay fault testability of 2-rail logic circuits. The flip flops used in the scan design are based on master-slave ones. The proposed scan design provides complete fault coverage in delay fault testing of 2-rail logic circuits. In two-pattern testing with the proposed scan design, initial vectors are set using the set-reset operation, and the scan-in operation for initial vectors is not required. Hence, the test application time is reduced to about half that of the enhanced scan design. Because the additional function is only the set-reset operation of the slave latch, the area overhead is small. The evaluation shows that the differences in the area overhead of the proposed scan design from those of the standard scan design and the enhanced scan design are 2.1 and -14.5 percent on average, respectively.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E92.D.336/_p
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@ARTICLE{e92-d_2_336,
author={Kentaroh KATOH, Kazuteru NAMBA, Hideo ITO, },
journal={IEICE TRANSACTIONS on Information},
title={Design for Delay Fault Testability of 2-Rail Logic Circuits},
year={2009},
volume={E92-D},
number={2},
pages={336-341},
abstract={This paper presents a scan design for delay fault testability of 2-rail logic circuits. The flip flops used in the scan design are based on master-slave ones. The proposed scan design provides complete fault coverage in delay fault testing of 2-rail logic circuits. In two-pattern testing with the proposed scan design, initial vectors are set using the set-reset operation, and the scan-in operation for initial vectors is not required. Hence, the test application time is reduced to about half that of the enhanced scan design. Because the additional function is only the set-reset operation of the slave latch, the area overhead is small. The evaluation shows that the differences in the area overhead of the proposed scan design from those of the standard scan design and the enhanced scan design are 2.1 and -14.5 percent on average, respectively.},
keywords={},
doi={10.1587/transinf.E92.D.336},
ISSN={1745-1361},
month={February},}
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TY - JOUR
TI - Design for Delay Fault Testability of 2-Rail Logic Circuits
T2 - IEICE TRANSACTIONS on Information
SP - 336
EP - 341
AU - Kentaroh KATOH
AU - Kazuteru NAMBA
AU - Hideo ITO
PY - 2009
DO - 10.1587/transinf.E92.D.336
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E92-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2009
AB - This paper presents a scan design for delay fault testability of 2-rail logic circuits. The flip flops used in the scan design are based on master-slave ones. The proposed scan design provides complete fault coverage in delay fault testing of 2-rail logic circuits. In two-pattern testing with the proposed scan design, initial vectors are set using the set-reset operation, and the scan-in operation for initial vectors is not required. Hence, the test application time is reduced to about half that of the enhanced scan design. Because the additional function is only the set-reset operation of the slave latch, the area overhead is small. The evaluation shows that the differences in the area overhead of the proposed scan design from those of the standard scan design and the enhanced scan design are 2.1 and -14.5 percent on average, respectively.
ER -