The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Les réseaux sur puces (NoC) sont des composants importants pour les processeurs multicœurs évolutifs. Étant donné que les performances des applications parallèles sont généralement sensibles à la latence des NoC, la réduire est une exigence primordiale. Dans cette étude, un routeur de compression qui masque le délai d’opération de (dé)compression est proposé. Le routeur de compression (dé)compresse le contenu du paquet entrant avant la fin de l'arbitrage de commutation, raccourcissant ainsi la longueur du paquet sans pénalité de latence et réduisant la latence d'injection et d'éjection du réseau. Les résultats de l'évaluation montrent que le routeur de compression améliore jusqu'à 33 % des performances des applications parallèles (gradients conjugués (CG), transformation de Fourier rapide (FT), tri d'entiers (IS) et problème du voyageur de commerce (TSP)) et 63 % des débit réseau effectif avec un taux de compression de 1.8 sur NoC. Le coût est une augmentation de la surface du routeur et de sa consommation d'énergie de 0.22 mm.2 et 1.6 fois par rapport au routeur à canal virtuel conventionnel. Une autre découverte est que le déchargement du décompresseur sur une interface réseau réduit la zone de compression du routeur de 57 % au détriment d'une augmentation modérée de la latence de communication.
Naoya NIWA
Keio University
Yoshiya SHIKAMA
Keio University
Hideharu AMANO
Keio University
Michihiro KOIBUCHI
National Institute of Informatics,PRESTO JST
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Naoya NIWA, Yoshiya SHIKAMA, Hideharu AMANO, Michihiro KOIBUCHI, "A Compression Router for Low-Latency Network-on-Chip" in IEICE TRANSACTIONS on Information,
vol. E106-D, no. 2, pp. 170-180, February 2023, doi: 10.1587/transinf.2022EDP7080.
Abstract: Network-on-Chips (NoCs) are important components for scalable many-core processors. Because the performance of parallel applications is usually sensitive to the latency of NoCs, reducing it is a primary requirement. In this study, a compression router that hides the (de)compression-operation delay is proposed. The compression router (de)compresses the contents of the incoming packet before the switch arbitration is completed, thus shortening the packet length without latency penalty and reducing the network injection-and-ejection latency. Evaluation results show that the compression router improves up to 33% of the parallel application performance (conjugate gradients (CG), fast Fourier transform (FT), integer sort (IS), and traveling salesman problem (TSP)) and 63% of the effective network throughput by 1.8 compression ratio on NoC. The cost is an increase in router area and its energy consumption by 0.22mm2 and 1.6 times compared to the conventional virtual-channel router. Another finding is that off-loading the decompressor onto a network interface decreases the compression-router area by 57% at the expense of the moderate increase in communication latency.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2022EDP7080/_p
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@ARTICLE{e106-d_2_170,
author={Naoya NIWA, Yoshiya SHIKAMA, Hideharu AMANO, Michihiro KOIBUCHI, },
journal={IEICE TRANSACTIONS on Information},
title={A Compression Router for Low-Latency Network-on-Chip},
year={2023},
volume={E106-D},
number={2},
pages={170-180},
abstract={Network-on-Chips (NoCs) are important components for scalable many-core processors. Because the performance of parallel applications is usually sensitive to the latency of NoCs, reducing it is a primary requirement. In this study, a compression router that hides the (de)compression-operation delay is proposed. The compression router (de)compresses the contents of the incoming packet before the switch arbitration is completed, thus shortening the packet length without latency penalty and reducing the network injection-and-ejection latency. Evaluation results show that the compression router improves up to 33% of the parallel application performance (conjugate gradients (CG), fast Fourier transform (FT), integer sort (IS), and traveling salesman problem (TSP)) and 63% of the effective network throughput by 1.8 compression ratio on NoC. The cost is an increase in router area and its energy consumption by 0.22mm2 and 1.6 times compared to the conventional virtual-channel router. Another finding is that off-loading the decompressor onto a network interface decreases the compression-router area by 57% at the expense of the moderate increase in communication latency.},
keywords={},
doi={10.1587/transinf.2022EDP7080},
ISSN={1745-1361},
month={February},}
Copier
TY - JOUR
TI - A Compression Router for Low-Latency Network-on-Chip
T2 - IEICE TRANSACTIONS on Information
SP - 170
EP - 180
AU - Naoya NIWA
AU - Yoshiya SHIKAMA
AU - Hideharu AMANO
AU - Michihiro KOIBUCHI
PY - 2023
DO - 10.1587/transinf.2022EDP7080
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E106-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2023
AB - Network-on-Chips (NoCs) are important components for scalable many-core processors. Because the performance of parallel applications is usually sensitive to the latency of NoCs, reducing it is a primary requirement. In this study, a compression router that hides the (de)compression-operation delay is proposed. The compression router (de)compresses the contents of the incoming packet before the switch arbitration is completed, thus shortening the packet length without latency penalty and reducing the network injection-and-ejection latency. Evaluation results show that the compression router improves up to 33% of the parallel application performance (conjugate gradients (CG), fast Fourier transform (FT), integer sort (IS), and traveling salesman problem (TSP)) and 63% of the effective network throughput by 1.8 compression ratio on NoC. The cost is an increase in router area and its energy consumption by 0.22mm2 and 1.6 times compared to the conventional virtual-channel router. Another finding is that off-loading the decompressor onto a network interface decreases the compression-router area by 57% at the expense of the moderate increase in communication latency.
ER -