The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article décrit la boucle à verrouillage de fréquence numérique (ADFLL) Fractional-N avec robustesse pour la variation PVT et son application pour l'unité de microcontrôleur. Le FLL conventionnel est difficile à atteindre les spécifications requises en utilisant le processus CMOS fin. En particulier, le FLL conventionnel présente certains problèmes tels qu'un fonctionnement inattendu et un long temps de verrouillage provoqués par la variation du PVT. Pour surmonter ces problèmes, nous proposons un nouvel ADFLL qui utilise des coefficients de filtre numérique à sélection dynamique. L'ADFLL proposé a été évalué via la simulation HSPICE et la fabrication de puces à l'aide d'un processus CMOS de 0.13 µm. À partir de ces résultats, nous avons observé que l'ADFLL proposé est robuste à la variation PVT en utilisant un coefficient de filtre numérique de sélection dynamique, et que le temps de verrouillage est amélioré jusqu'à 57 %, la gigue d'horloge est de 0.85 ns.
Ryoichi MIYAUCHI
Tokyo University of Science
Akio YOSHIDA
ROHM Co., Ltd.
Shuya NAKANO
University of Miyazaki
Hiroki TAMURA
University of Miyazaki
Koichi TANNO
University of Miyazaki
Yutaka FUKUCHI
Tokyo University of Science
Yukio KAWAMURA
LAPIS Semiconductor Co., Ltd.
Yuki KODAMA
LAPIS Semiconductor Co., Ltd.
Yuichi SEKIYA
LAPIS Semiconductor Co., Ltd.
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Ryoichi MIYAUCHI, Akio YOSHIDA, Shuya NAKANO, Hiroki TAMURA, Koichi TANNO, Yutaka FUKUCHI, Yukio KAWAMURA, Yuki KODAMA, Yuichi SEKIYA, "The Fractional-N All Digital Frequency Locked Loop with Robustness for PVT Variation and Its Application for the Microcontroller Unit" in IEICE TRANSACTIONS on Information,
vol. E104-D, no. 8, pp. 1146-1153, August 2021, doi: 10.1587/transinf.2020LOP0008.
Abstract: This paper describes the Fractional-N All Digital Frequency Locked Loop (ADFLL) with Robustness for PVT variation and its application for the microcontroller unit. The conventional FLL is difficult to achieve the required specification by using the fine CMOS process. Especially, the conventional FLL has some problems such as unexpected operation and long lock time that are caused by PVT variation. To overcome these problems, we propose a new ADFLL which uses dynamic selecting digital filter coefficients. The proposed ADFLL was evaluatied through the HSPICE simulation and fabricating chips using a 0.13 µm CMOS process. From these results, we observed the proposed ADFLL has robustness for PVT variation by using dynamic selecting digital filter coefficient, and the lock time is improved up to 57%, clock jitter is 0.85 nsec.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2020LOP0008/_p
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@ARTICLE{e104-d_8_1146,
author={Ryoichi MIYAUCHI, Akio YOSHIDA, Shuya NAKANO, Hiroki TAMURA, Koichi TANNO, Yutaka FUKUCHI, Yukio KAWAMURA, Yuki KODAMA, Yuichi SEKIYA, },
journal={IEICE TRANSACTIONS on Information},
title={The Fractional-N All Digital Frequency Locked Loop with Robustness for PVT Variation and Its Application for the Microcontroller Unit},
year={2021},
volume={E104-D},
number={8},
pages={1146-1153},
abstract={This paper describes the Fractional-N All Digital Frequency Locked Loop (ADFLL) with Robustness for PVT variation and its application for the microcontroller unit. The conventional FLL is difficult to achieve the required specification by using the fine CMOS process. Especially, the conventional FLL has some problems such as unexpected operation and long lock time that are caused by PVT variation. To overcome these problems, we propose a new ADFLL which uses dynamic selecting digital filter coefficients. The proposed ADFLL was evaluatied through the HSPICE simulation and fabricating chips using a 0.13 µm CMOS process. From these results, we observed the proposed ADFLL has robustness for PVT variation by using dynamic selecting digital filter coefficient, and the lock time is improved up to 57%, clock jitter is 0.85 nsec.},
keywords={},
doi={10.1587/transinf.2020LOP0008},
ISSN={1745-1361},
month={August},}
Copier
TY - JOUR
TI - The Fractional-N All Digital Frequency Locked Loop with Robustness for PVT Variation and Its Application for the Microcontroller Unit
T2 - IEICE TRANSACTIONS on Information
SP - 1146
EP - 1153
AU - Ryoichi MIYAUCHI
AU - Akio YOSHIDA
AU - Shuya NAKANO
AU - Hiroki TAMURA
AU - Koichi TANNO
AU - Yutaka FUKUCHI
AU - Yukio KAWAMURA
AU - Yuki KODAMA
AU - Yuichi SEKIYA
PY - 2021
DO - 10.1587/transinf.2020LOP0008
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E104-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2021
AB - This paper describes the Fractional-N All Digital Frequency Locked Loop (ADFLL) with Robustness for PVT variation and its application for the microcontroller unit. The conventional FLL is difficult to achieve the required specification by using the fine CMOS process. Especially, the conventional FLL has some problems such as unexpected operation and long lock time that are caused by PVT variation. To overcome these problems, we propose a new ADFLL which uses dynamic selecting digital filter coefficients. The proposed ADFLL was evaluatied through the HSPICE simulation and fabricating chips using a 0.13 µm CMOS process. From these results, we observed the proposed ADFLL has robustness for PVT variation by using dynamic selecting digital filter coefficient, and the lock time is improved up to 57%, clock jitter is 0.85 nsec.
ER -