The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dans les systèmes informatiques parallèles, le réseau d'interconnexion constitue l'infrastructure critique qui permet une communication robuste et évolutive entre des centaines de milliers de nœuds. Le réseau traditionnel à commutation de paquets a tendance à souffrir d'un long temps de communication en cas de congestion du réseau. Dans ce contexte, nous explorons l'utilisation de la commutation de circuits (CS) pour remplacer les commutateurs de paquets par du matériel personnalisé prenant en charge efficacement la commutation basée sur les circuits avec une faible latence. Dans notre réseau CS cible, une certaine quantité de bande passante est garantie pour chaque paire de communication afin que la latence du réseau puisse être prévisible lorsqu'un nombre limité de paires de nœuds échangent des messages. Le nombre d'intervalles de temps alloués dans chaque commutateur est un facteur direct qui affecte la latence de bout en bout. Nous améliorons ainsi l'utilisation des emplacements et développons un générateur de topologie de réseau pour minimiser le nombre d'intervalles de temps optimisés pour cibler les applications dont les modèles de communication sont prévisible. Par une simulation quantitative à événements discrets, nous illustrons que le nombre minimum nécessaire de slots peut être réduit à un petit nombre dans une topologie générée par notre méthodologie de conception tout en maintenant un coût de réseau 50 % inférieur à celui des topologies tori standard.
Yao HU
National Institute of Informatics
Michihiro KOIBUCHI
National Institute of Informatics
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Yao HU, Michihiro KOIBUCHI, "Optimizing Slot Utilization and Network Topology for Communication Pattern on Circuit-Switched Parallel Computing Systems" in IEICE TRANSACTIONS on Information,
vol. E102-D, no. 2, pp. 247-260, February 2019, doi: 10.1587/transinf.2018EDP7225.
Abstract: In parallel computing systems, the interconnection network forms the critical infrastructure which enables robust and scalable communication between hundreds of thousands of nodes. The traditional packet-switched network tends to suffer from long communication time when network congestion occurs. In this context, we explore the use of circuit switching (CS) to replace packet switches with custom hardware that supports circuit-based switching efficiently with low latency. In our target CS network, a certain amount of bandwidth is guaranteed for each communication pair so that the network latency can be predictable when a limited number of node pairs exchange messages. The number of allocated time slots in every switch is a direct factor to affect the end-to-end latency, we thereby improve the slot utilization and develop a network topology generator to minimize the number of time slots optimized to target applications whose communication patterns are predictable. By a quantitative discrete-event simulation, we illustrate that the minimum necessary number of slots can be reduced to a small number in a generated topology by our design methodology while maintaining network cost 50% less than that in standard tori topologies.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2018EDP7225/_p
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@ARTICLE{e102-d_2_247,
author={Yao HU, Michihiro KOIBUCHI, },
journal={IEICE TRANSACTIONS on Information},
title={Optimizing Slot Utilization and Network Topology for Communication Pattern on Circuit-Switched Parallel Computing Systems},
year={2019},
volume={E102-D},
number={2},
pages={247-260},
abstract={In parallel computing systems, the interconnection network forms the critical infrastructure which enables robust and scalable communication between hundreds of thousands of nodes. The traditional packet-switched network tends to suffer from long communication time when network congestion occurs. In this context, we explore the use of circuit switching (CS) to replace packet switches with custom hardware that supports circuit-based switching efficiently with low latency. In our target CS network, a certain amount of bandwidth is guaranteed for each communication pair so that the network latency can be predictable when a limited number of node pairs exchange messages. The number of allocated time slots in every switch is a direct factor to affect the end-to-end latency, we thereby improve the slot utilization and develop a network topology generator to minimize the number of time slots optimized to target applications whose communication patterns are predictable. By a quantitative discrete-event simulation, we illustrate that the minimum necessary number of slots can be reduced to a small number in a generated topology by our design methodology while maintaining network cost 50% less than that in standard tori topologies.},
keywords={},
doi={10.1587/transinf.2018EDP7225},
ISSN={1745-1361},
month={February},}
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TY - JOUR
TI - Optimizing Slot Utilization and Network Topology for Communication Pattern on Circuit-Switched Parallel Computing Systems
T2 - IEICE TRANSACTIONS on Information
SP - 247
EP - 260
AU - Yao HU
AU - Michihiro KOIBUCHI
PY - 2019
DO - 10.1587/transinf.2018EDP7225
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E102-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2019
AB - In parallel computing systems, the interconnection network forms the critical infrastructure which enables robust and scalable communication between hundreds of thousands of nodes. The traditional packet-switched network tends to suffer from long communication time when network congestion occurs. In this context, we explore the use of circuit switching (CS) to replace packet switches with custom hardware that supports circuit-based switching efficiently with low latency. In our target CS network, a certain amount of bandwidth is guaranteed for each communication pair so that the network latency can be predictable when a limited number of node pairs exchange messages. The number of allocated time slots in every switch is a direct factor to affect the end-to-end latency, we thereby improve the slot utilization and develop a network topology generator to minimize the number of time slots optimized to target applications whose communication patterns are predictable. By a quantitative discrete-event simulation, we illustrate that the minimum necessary number of slots can be reduced to a small number in a generated topology by our design methodology while maintaining network cost 50% less than that in standard tori topologies.
ER -