The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Un réseau d'accès à la mémoire optique de faible puissance optimisé est proposé pour réduire le coût des résonateurs à microanneaux (MR) dans les systèmes kilocœurs, tels que la perte de passage et la difficulté d'intégration. Par rapport à l'interconnexion de bus électronique traditionnelle, le réseau proposé réduit la consommation d'énergie et la latence de 80 à 89 % et de 21 à 24 %. De plus, le nouveau réseau réduit le nombre de MR de 90.6 % sans augmentation de la consommation d'énergie et de la latence par rapport au réseau en anneau optique sur puce (ORNoC).
Tao LIU
Xidian University
Huaxi GU
Xidian University
Yue WANG
Xidian University
Wei ZOU
Xidian University
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copier
Tao LIU, Huaxi GU, Yue WANG, Wei ZOU, "An Optimized Low-Power Optical Memory Access Network for Kilocore Systems" in IEICE TRANSACTIONS on Information,
vol. E102-D, no. 5, pp. 1085-1088, May 2019, doi: 10.1587/transinf.2018EDL8234.
Abstract: An optimized low-power optical memory access network is proposed to alleviate the cost of microring resonators (MRs) in kilocore systems, such as the pass-by loss and integration difficulty. Compared with traditional electronic bus interconnect, the proposed network reduces power consumption and latency by 80% to 89% and 21% to 24%. Moreover, the new network decreases the number of MRs by 90.6% without an increase in power consumption and latency when making a comparison with Optical Ring Network-on-Chip (ORNoC).
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2018EDL8234/_p
Copier
@ARTICLE{e102-d_5_1085,
author={Tao LIU, Huaxi GU, Yue WANG, Wei ZOU, },
journal={IEICE TRANSACTIONS on Information},
title={An Optimized Low-Power Optical Memory Access Network for Kilocore Systems},
year={2019},
volume={E102-D},
number={5},
pages={1085-1088},
abstract={An optimized low-power optical memory access network is proposed to alleviate the cost of microring resonators (MRs) in kilocore systems, such as the pass-by loss and integration difficulty. Compared with traditional electronic bus interconnect, the proposed network reduces power consumption and latency by 80% to 89% and 21% to 24%. Moreover, the new network decreases the number of MRs by 90.6% without an increase in power consumption and latency when making a comparison with Optical Ring Network-on-Chip (ORNoC).},
keywords={},
doi={10.1587/transinf.2018EDL8234},
ISSN={1745-1361},
month={May},}
Copier
TY - JOUR
TI - An Optimized Low-Power Optical Memory Access Network for Kilocore Systems
T2 - IEICE TRANSACTIONS on Information
SP - 1085
EP - 1088
AU - Tao LIU
AU - Huaxi GU
AU - Yue WANG
AU - Wei ZOU
PY - 2019
DO - 10.1587/transinf.2018EDL8234
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E102-D
IS - 5
JA - IEICE TRANSACTIONS on Information
Y1 - May 2019
AB - An optimized low-power optical memory access network is proposed to alleviate the cost of microring resonators (MRs) in kilocore systems, such as the pass-by loss and integration difficulty. Compared with traditional electronic bus interconnect, the proposed network reduces power consumption and latency by 80% to 89% and 21% to 24%. Moreover, the new network decreases the number of MRs by 90.6% without an increase in power consumption and latency when making a comparison with Optical Ring Network-on-Chip (ORNoC).
ER -