The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
An n-les tests de détection des défauts bloqués peuvent être utilisés non seulement pour les tests de défauts retardés, mais également pour la détection de défauts non modélisés. Nous avons développé un circuit BIST hybride ; c'est-à-dire une méthode composée d'un registre à décalage avec rotation partielle et d'une procédure qui sélectionne les vecteurs de test parmi ceux de l'ATPG. Cette méthode de test peut effectuer des tests à vitesse élevée avec une couverture élevée des défauts bloqués. Pendant les tests à vitesse élevée, un sous-ensemble des vecteurs ATPG est saisi à l'aide d'un testeur à basse vitesse. Des simulations informatiques sur les circuits ISCAS'85, ISCAS'89 et ITC'99 sont réalisées pour n = 1, 2, 3, 5, 10 et 15. Les résultats de la simulation montrent que la quantité de vecteurs de test peut être réduite entre 52.3 % et 0.9 % par rapport à celle des vecteurs ATPG. En conséquence, la méthode proposée peut réduire le coût des tests à vitesse élevée.
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Kenichi ICHINO, Takeshi ASAKAWA, Satoshi FUKUMOTO, Kazuhiko IWASAKI, Seiji KAJIHARA, "Hybrid BIST Design for n-Detection Test Using Partially Rotational Scan" in IEICE TRANSACTIONS on Information,
vol. E85-D, no. 10, pp. 1490-1497, October 2002, doi: .
Abstract: An n-detection testing for stuck-at faults can be used not only for delay fault testing but also for detection of unmodeled faults. We have developed a hybrid BIST circuit; that is, a method consisting of a shift register with partial rotation and a procedure that selects test vectors from ATPG ones. This testing method can perform at-speed testing with high stuck-at fault coverage. During the at-speed testing, a subset of the ATPG vectors is input by using a low-speed tester. Computer simulations on ISCAS'85, ISCAS'89, and ITC'99 circuits are conducted for n = 1, 2, 3, 5, 10, and 15. The simulation results show that the amount of test vectors can be reduced to ranging from 52.3% to 0.9% in comparison with that of the ATPG vectors. As a result, the proposed method can reduce the cost of at-speed testing.
URL: https://global.ieice.org/en_transactions/information/10.1587/e85-d_10_1490/_p
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@ARTICLE{e85-d_10_1490,
author={Kenichi ICHINO, Takeshi ASAKAWA, Satoshi FUKUMOTO, Kazuhiko IWASAKI, Seiji KAJIHARA, },
journal={IEICE TRANSACTIONS on Information},
title={Hybrid BIST Design for n-Detection Test Using Partially Rotational Scan},
year={2002},
volume={E85-D},
number={10},
pages={1490-1497},
abstract={An n-detection testing for stuck-at faults can be used not only for delay fault testing but also for detection of unmodeled faults. We have developed a hybrid BIST circuit; that is, a method consisting of a shift register with partial rotation and a procedure that selects test vectors from ATPG ones. This testing method can perform at-speed testing with high stuck-at fault coverage. During the at-speed testing, a subset of the ATPG vectors is input by using a low-speed tester. Computer simulations on ISCAS'85, ISCAS'89, and ITC'99 circuits are conducted for n = 1, 2, 3, 5, 10, and 15. The simulation results show that the amount of test vectors can be reduced to ranging from 52.3% to 0.9% in comparison with that of the ATPG vectors. As a result, the proposed method can reduce the cost of at-speed testing.},
keywords={},
doi={},
ISSN={},
month={October},}
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TY - JOUR
TI - Hybrid BIST Design for n-Detection Test Using Partially Rotational Scan
T2 - IEICE TRANSACTIONS on Information
SP - 1490
EP - 1497
AU - Kenichi ICHINO
AU - Takeshi ASAKAWA
AU - Satoshi FUKUMOTO
AU - Kazuhiko IWASAKI
AU - Seiji KAJIHARA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E85-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2002
AB - An n-detection testing for stuck-at faults can be used not only for delay fault testing but also for detection of unmodeled faults. We have developed a hybrid BIST circuit; that is, a method consisting of a shift register with partial rotation and a procedure that selects test vectors from ATPG ones. This testing method can perform at-speed testing with high stuck-at fault coverage. During the at-speed testing, a subset of the ATPG vectors is input by using a low-speed tester. Computer simulations on ISCAS'85, ISCAS'89, and ITC'99 circuits are conducted for n = 1, 2, 3, 5, 10, and 15. The simulation results show that the amount of test vectors can be reduced to ranging from 52.3% to 0.9% in comparison with that of the ATPG vectors. As a result, the proposed method can reduce the cost of at-speed testing.
ER -