The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dans cet article, nous proposons le système de raisonnement évolutif basé sur un algorithme et sa méthodologie de conception. Dans la méthodologie de conception proposée, les règles de raisonnement derrière les cas passés dans chaque tâche (dans chaque base de données de cas) sont extraites via des algorithmes génétiques et sont exprimées sous forme de tables de vérité (nous les appelons « tables de vérité évoluées »). Les circuits des systèmes de raisonnement sont synthétisés à partir des tables de vérité évoluées. Le parallélisme dans chaque tâche peut être intégré directement dans les circuits par l'implémentation matérielle des tables de vérité évoluées, de sorte qu'un système de raisonnement à grande vitesse avec une taille matérielle petite ou acceptable soit obtenu. Nous avons développé un système prototype utilisant des puces FPGA Xilinx Virtex et l'avons appliqué au raisonnement par limites génétiques (GBR) et au raisonnement par prononciation anglaise (EPR), qui sont des tâches pratiques très importantes dans le domaine de la science du génome et du traitement du langage, respectivement. Les systèmes prototypes GBR et EPR sont évalués en termes de précision du raisonnement, de taille de circuit et de vitesse de traitement, et comparés aux approches conventionnelles de l'IA parallèle et des réseaux de neurones artificiels. Des expériences d'injection de fautes sont également réalisées à l'aide du système prototype, et sa haute tolérance aux pannes, ou dégradation gracieuse contre des circuits défectueux qui convient à la mise en œuvre matérielle utilisant des LSI à l'échelle d'une tranche, est démontrée.
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Moritoshi YASUNAGA, Ikuo YOSHIHARA, Jung Hwan KIM, "The Evolutionary Algorithm-Based Reasoning System" in IEICE TRANSACTIONS on Information,
vol. E84-D, no. 11, pp. 1508-1520, November 2001, doi: .
Abstract: In this paper, we propose the evolutionary algorithm-based reasoning system and its design methodology. In the proposed design methodology, reasoning rules behind the past cases in each task (in each case database) are extracted through genetic algorithms and are expressed as truth tables (we call them 'evolved truth tables'). Circuits for the reasoning systems are synthesized from the evolved truth tables. Parallelism in each task can be embedded directly in the circuits by the hardware implementation of the evolved truth tables, so that the high speed reasoning system with small or acceptable hardware size is achieved. We developed a prototype system using Xilinx Virtex FPGA chips and applied it to the gene boundary reasoning (GBR) and English pronunciation reasoning (EPR), which are very important practical tasks in the genome science and language processing field, respectively. The GBR and the EPR prototype systems are evaluated in terms of the reasoning accuracy, circuit size, and processing speed, and compared with the conventional approaches in the parallel AI and the artificial neural networks. Fault injection experiments are also carried out using the prototype system, and its high fault-tolerance, or graceful degradation against defective circuits that suits to the hardware implementation using wafer scale LSIs is demonstrated.
URL: https://global.ieice.org/en_transactions/information/10.1587/e84-d_11_1508/_p
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@ARTICLE{e84-d_11_1508,
author={Moritoshi YASUNAGA, Ikuo YOSHIHARA, Jung Hwan KIM, },
journal={IEICE TRANSACTIONS on Information},
title={The Evolutionary Algorithm-Based Reasoning System},
year={2001},
volume={E84-D},
number={11},
pages={1508-1520},
abstract={In this paper, we propose the evolutionary algorithm-based reasoning system and its design methodology. In the proposed design methodology, reasoning rules behind the past cases in each task (in each case database) are extracted through genetic algorithms and are expressed as truth tables (we call them 'evolved truth tables'). Circuits for the reasoning systems are synthesized from the evolved truth tables. Parallelism in each task can be embedded directly in the circuits by the hardware implementation of the evolved truth tables, so that the high speed reasoning system with small or acceptable hardware size is achieved. We developed a prototype system using Xilinx Virtex FPGA chips and applied it to the gene boundary reasoning (GBR) and English pronunciation reasoning (EPR), which are very important practical tasks in the genome science and language processing field, respectively. The GBR and the EPR prototype systems are evaluated in terms of the reasoning accuracy, circuit size, and processing speed, and compared with the conventional approaches in the parallel AI and the artificial neural networks. Fault injection experiments are also carried out using the prototype system, and its high fault-tolerance, or graceful degradation against defective circuits that suits to the hardware implementation using wafer scale LSIs is demonstrated.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - The Evolutionary Algorithm-Based Reasoning System
T2 - IEICE TRANSACTIONS on Information
SP - 1508
EP - 1520
AU - Moritoshi YASUNAGA
AU - Ikuo YOSHIHARA
AU - Jung Hwan KIM
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E84-D
IS - 11
JA - IEICE TRANSACTIONS on Information
Y1 - November 2001
AB - In this paper, we propose the evolutionary algorithm-based reasoning system and its design methodology. In the proposed design methodology, reasoning rules behind the past cases in each task (in each case database) are extracted through genetic algorithms and are expressed as truth tables (we call them 'evolved truth tables'). Circuits for the reasoning systems are synthesized from the evolved truth tables. Parallelism in each task can be embedded directly in the circuits by the hardware implementation of the evolved truth tables, so that the high speed reasoning system with small or acceptable hardware size is achieved. We developed a prototype system using Xilinx Virtex FPGA chips and applied it to the gene boundary reasoning (GBR) and English pronunciation reasoning (EPR), which are very important practical tasks in the genome science and language processing field, respectively. The GBR and the EPR prototype systems are evaluated in terms of the reasoning accuracy, circuit size, and processing speed, and compared with the conventional approaches in the parallel AI and the artificial neural networks. Fault injection experiments are also carried out using the prototype system, and its high fault-tolerance, or graceful degradation against defective circuits that suits to the hardware implementation using wafer scale LSIs is demonstrated.
ER -