The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article présente une nouvelle conception pour tester les réseaux prédiffusés programmables sur site (FPGA) basés sur SRAM. La mémoire SRAM du FPGA d'origine est modifiée afin que le FPGA puisse avoir la possibilité de boucler les données de configuration de test à l'intérieur de la puce. Le test complet du FPGA est réalisé en chargeant généralement une seule donnée de configuration de test soigneusement choisie au lieu de l'ensemble des données de configuration. Les autres données de configuration requises sont obtenues en déplaçant la première à l'intérieur de la puce. En conséquence, le test devient plus rapide. Cette méthode ne nécessite pas une grande mémoire hors puce pour le test. Les résultats de l'évaluation prouvent que cette méthode est très efficace lorsque la complexité des blocs configurables (CLB) ou la taille des puces augmente.
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Abderrahim DOUMAR, Toshiaki OHMAMEUDA, Hideo ITO, "Fast Testable Design for SRAM-Based FPGAs" in IEICE TRANSACTIONS on Information,
vol. E83-D, no. 5, pp. 1116-1127, May 2000, doi: .
Abstract: This paper presents a new design for testing SRAM-based field programmable gate arrays (FPGAs). The original FPGA's SRAM memory is modified so that the FPGA may have the facility to loop the testing configuration data inside the chip. The full testing of the FPGA is achieved by loading typically only one carefully chosen testing configuration data instead of the whole configurations data. The other required configurations data are obtained by shifting the first one inside the chip. As a result, the test becomes faster. This method does not need a large off-chip memory for the test. The evaluation results prove that this method is very effective when the complexity of the configurable blocks (CLBs) or the chip size increases.
URL: https://global.ieice.org/en_transactions/information/10.1587/e83-d_5_1116/_p
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@ARTICLE{e83-d_5_1116,
author={Abderrahim DOUMAR, Toshiaki OHMAMEUDA, Hideo ITO, },
journal={IEICE TRANSACTIONS on Information},
title={Fast Testable Design for SRAM-Based FPGAs},
year={2000},
volume={E83-D},
number={5},
pages={1116-1127},
abstract={This paper presents a new design for testing SRAM-based field programmable gate arrays (FPGAs). The original FPGA's SRAM memory is modified so that the FPGA may have the facility to loop the testing configuration data inside the chip. The full testing of the FPGA is achieved by loading typically only one carefully chosen testing configuration data instead of the whole configurations data. The other required configurations data are obtained by shifting the first one inside the chip. As a result, the test becomes faster. This method does not need a large off-chip memory for the test. The evaluation results prove that this method is very effective when the complexity of the configurable blocks (CLBs) or the chip size increases.},
keywords={},
doi={},
ISSN={},
month={May},}
Copier
TY - JOUR
TI - Fast Testable Design for SRAM-Based FPGAs
T2 - IEICE TRANSACTIONS on Information
SP - 1116
EP - 1127
AU - Abderrahim DOUMAR
AU - Toshiaki OHMAMEUDA
AU - Hideo ITO
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E83-D
IS - 5
JA - IEICE TRANSACTIONS on Information
Y1 - May 2000
AB - This paper presents a new design for testing SRAM-based field programmable gate arrays (FPGAs). The original FPGA's SRAM memory is modified so that the FPGA may have the facility to loop the testing configuration data inside the chip. The full testing of the FPGA is achieved by loading typically only one carefully chosen testing configuration data instead of the whole configurations data. The other required configurations data are obtained by shifting the first one inside the chip. As a result, the test becomes faster. This method does not need a large off-chip memory for the test. The evaluation results prove that this method is very effective when the complexity of the configurable blocks (CLBs) or the chip size increases.
ER -