The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Le modèle Scalable-Delay-Insensitive (SDI) est proposé pour la conception de systèmes asynchrones hautes performances. Dans cet article, nous nous concentrons sur la vérification si un circuit sous le modèle SDI satisfait certaines propriétés non temporisées, et montrons formellement que la vérification de ces propriétés dans le modèle SDI peut être réduite à la vérification des mêmes propriétés dans le modèle à retard borné. Ce résultat suggère que les algorithmes de vérification existants pour le modèle à retard borné peuvent être utilisés pour la vérification des circuits SDI, ce qui aide considérablement les concepteurs de circuits SDI.
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Atsushi YAMAZAKI, Hiroshi RYU, Tomohiro YONEDA, "Verification of Scalable-Delay-Insensitive Asynchronous Circuits" in IEICE TRANSACTIONS on Information,
vol. E82-D, no. 3, pp. 701-703, March 1999, doi: .
Abstract: The Scalable-Delay-Insensitive (SDI) model is proposed for high-performance asynchronous system design. In this paper, we focus on checking whether a circuit under SDI model satisfies some untimed properties, and formally show that checking these properties in the SDI model can be reduced to checking the same properties in the bounded delay model. This result suggests that the existing verification algorithms for the bounded delay model can be used for the verification of SDI circuits, which significantly helps the designers of SDI circuits.
URL: https://global.ieice.org/en_transactions/information/10.1587/e82-d_3_701/_p
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@ARTICLE{e82-d_3_701,
author={Atsushi YAMAZAKI, Hiroshi RYU, Tomohiro YONEDA, },
journal={IEICE TRANSACTIONS on Information},
title={Verification of Scalable-Delay-Insensitive Asynchronous Circuits},
year={1999},
volume={E82-D},
number={3},
pages={701-703},
abstract={The Scalable-Delay-Insensitive (SDI) model is proposed for high-performance asynchronous system design. In this paper, we focus on checking whether a circuit under SDI model satisfies some untimed properties, and formally show that checking these properties in the SDI model can be reduced to checking the same properties in the bounded delay model. This result suggests that the existing verification algorithms for the bounded delay model can be used for the verification of SDI circuits, which significantly helps the designers of SDI circuits.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - Verification of Scalable-Delay-Insensitive Asynchronous Circuits
T2 - IEICE TRANSACTIONS on Information
SP - 701
EP - 703
AU - Atsushi YAMAZAKI
AU - Hiroshi RYU
AU - Tomohiro YONEDA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E82-D
IS - 3
JA - IEICE TRANSACTIONS on Information
Y1 - March 1999
AB - The Scalable-Delay-Insensitive (SDI) model is proposed for high-performance asynchronous system design. In this paper, we focus on checking whether a circuit under SDI model satisfies some untimed properties, and formally show that checking these properties in the SDI model can be reduced to checking the same properties in the bounded delay model. This result suggests that the existing verification algorithms for the bounded delay model can be used for the verification of SDI circuits, which significantly helps the designers of SDI circuits.
ER -