The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
A. Chatterjee et coll. tests proposés avec propriété de linéarité pour les défauts de retard de porte afin de déterminer, à une vitesse d'horloge requise, si un circuit testé est une puce marginale ou non. Le dernier temps de transition à la sortie primaire est modifié linéairement en fonction de la taille du défaut de retard de grille lorsque le test proposé est appliqué au circuit testé. À la connaissance des auteurs, aucun rapport sur une méthode algorithmique de génération de tests avec propriété de linéarité n’a été présenté auparavant. Dans cet article, nous proposons une méthode pour générer des tests avec propriété de linéarité pour les défauts de retard de porte. La méthode proposée introduit un nouveau calcul temporisé étendu pour calculer la taille d'un défaut de retard de porte donné qui peut se propager à la sortie primaire. La méthode a été appliquée aux circuits de référence ISCAS selon le modèle de retard unitaire.
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Hiroshi TAKAHASHI, Kwame Osei BOATENG, Yuzo TAKAMATSU, "A Method of Generating Tests with Linearity Property for Gate Delay Faults in Combinational Circuits" in IEICE TRANSACTIONS on Information,
vol. E82-D, no. 11, pp. 1466-1473, November 1999, doi: .
Abstract: A. Chatterjee et al. proposed tests with linearity property for gate delay faults to determine, at a required clock speed, whether a circuit under test is a marginal chip or not. The latest transition time at the primary output is changed linearly with the size of the gate delay fault when the proposed test is applied to the circuit under test. To authors' knowledge, no reports on an algorithmic method for generating tests with linearity property have been presented before. In this paper, we propose a method for generating tests with linearity property for gate delay faults. The proposed method introduces a new extended timed calculus to calculate the size of a given gate delay fault that can be propagated to the primary output. The method has been applied to ISCAS benchmark circuits under the unit delay model.
URL: https://global.ieice.org/en_transactions/information/10.1587/e82-d_11_1466/_p
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@ARTICLE{e82-d_11_1466,
author={Hiroshi TAKAHASHI, Kwame Osei BOATENG, Yuzo TAKAMATSU, },
journal={IEICE TRANSACTIONS on Information},
title={A Method of Generating Tests with Linearity Property for Gate Delay Faults in Combinational Circuits},
year={1999},
volume={E82-D},
number={11},
pages={1466-1473},
abstract={A. Chatterjee et al. proposed tests with linearity property for gate delay faults to determine, at a required clock speed, whether a circuit under test is a marginal chip or not. The latest transition time at the primary output is changed linearly with the size of the gate delay fault when the proposed test is applied to the circuit under test. To authors' knowledge, no reports on an algorithmic method for generating tests with linearity property have been presented before. In this paper, we propose a method for generating tests with linearity property for gate delay faults. The proposed method introduces a new extended timed calculus to calculate the size of a given gate delay fault that can be propagated to the primary output. The method has been applied to ISCAS benchmark circuits under the unit delay model.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - A Method of Generating Tests with Linearity Property for Gate Delay Faults in Combinational Circuits
T2 - IEICE TRANSACTIONS on Information
SP - 1466
EP - 1473
AU - Hiroshi TAKAHASHI
AU - Kwame Osei BOATENG
AU - Yuzo TAKAMATSU
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E82-D
IS - 11
JA - IEICE TRANSACTIONS on Information
Y1 - November 1999
AB - A. Chatterjee et al. proposed tests with linearity property for gate delay faults to determine, at a required clock speed, whether a circuit under test is a marginal chip or not. The latest transition time at the primary output is changed linearly with the size of the gate delay fault when the proposed test is applied to the circuit under test. To authors' knowledge, no reports on an algorithmic method for generating tests with linearity property have been presented before. In this paper, we propose a method for generating tests with linearity property for gate delay faults. The proposed method introduces a new extended timed calculus to calculate the size of a given gate delay fault that can be propagated to the primary output. The method has been applied to ISCAS benchmark circuits under the unit delay model.
ER -