The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dans cet article, un schéma de cache d'instructions appelé Multi-Path Tracing est proposé pour améliorer le cache de trace. Les chemins sont classés pour améliorer le taux de réussite du cache de trace en réduisant le conflit de chemin et les blocs de base sont joints pour réduire le coût matériel nécessaire à la mise en œuvre du cache de trace. Les résultats de simulation pour divers benchmarks entiers SPEC montrent que le schéma proposé augmente le taux de réussite de plus de 25 % et la taille de récupération effective de 10 %.
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Jin-Hyuk YANG, In-Cheol PARK, Chong-Min KYUNG, "Path-Classified Trace Cache for Improving Hit Ratio in Wide-Issue Processors" in IEICE TRANSACTIONS on Information,
vol. E82-D, no. 10, pp. 1338-1343, October 1999, doi: .
Abstract: In this paper, an instruction-cache scheme called Multi-Path Tracing is proposed to enhance the trace cache. Paths are classified to improve the trace cache hit ratio by reducing the path conflict and basic blocks are joined to reduce the hardware cost needed to implement the trace cache. Simulation results for various SPEC integer benchmarks show that the proposed scheme increases the hit ratio by more than 25% and the effective fetch size by 10%.
URL: https://global.ieice.org/en_transactions/information/10.1587/e82-d_10_1338/_p
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@ARTICLE{e82-d_10_1338,
author={Jin-Hyuk YANG, In-Cheol PARK, Chong-Min KYUNG, },
journal={IEICE TRANSACTIONS on Information},
title={Path-Classified Trace Cache for Improving Hit Ratio in Wide-Issue Processors},
year={1999},
volume={E82-D},
number={10},
pages={1338-1343},
abstract={In this paper, an instruction-cache scheme called Multi-Path Tracing is proposed to enhance the trace cache. Paths are classified to improve the trace cache hit ratio by reducing the path conflict and basic blocks are joined to reduce the hardware cost needed to implement the trace cache. Simulation results for various SPEC integer benchmarks show that the proposed scheme increases the hit ratio by more than 25% and the effective fetch size by 10%.},
keywords={},
doi={},
ISSN={},
month={October},}
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TY - JOUR
TI - Path-Classified Trace Cache for Improving Hit Ratio in Wide-Issue Processors
T2 - IEICE TRANSACTIONS on Information
SP - 1338
EP - 1343
AU - Jin-Hyuk YANG
AU - In-Cheol PARK
AU - Chong-Min KYUNG
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E82-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 1999
AB - In this paper, an instruction-cache scheme called Multi-Path Tracing is proposed to enhance the trace cache. Paths are classified to improve the trace cache hit ratio by reducing the path conflict and basic blocks are joined to reduce the hardware cost needed to implement the trace cache. Simulation results for various SPEC integer benchmarks show that the proposed scheme increases the hit ratio by more than 25% and the effective fetch size by 10%.
ER -