The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
MD5 est un algorithme cryptographique utilisé pour l'authentification. Lorsqu'elles sont implémentées dans le matériel, les performances sont affectées par la dépendance aux données de la fonction de compression itérative. Dans cet article, une nouvelle description fonctionnelle est proposée dans le but d'atteindre un débit plus élevé en réduisant le chemin critique et la latence. Cette description peut être utilisée dans des structures similaires d'autres algorithmes de hachage, tels que SHA-1, SHA-2 et RIPEMD-160, qui ont une dépendance aux données comparable. L'architecture matérielle MD5 proposée atteint un rapport débit/surface élevé, les résultats de la mise en œuvre dans un FPGA sont présentés et discutés, ainsi que des comparaisons avec des travaux connexes.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copier
Ignacio ALGREDO-BADILLO, Claudia FEREGRINO-URIBE, Rene CUMPLIDO, Miguel MORALES-SANDOVAL, "Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description" in IEICE TRANSACTIONS on Information,
vol. E91-D, no. 10, pp. 2519-2523, October 2008, doi: 10.1093/ietisy/e91-d.10.2519.
Abstract: MD5 is a cryptographic algorithm used for authentication. When implemented in hardware, the performance is affected by the data dependency of the iterative compression function. In this paper, a new functional description is proposed with the aim of achieving higher throughput by mean of reducing the critical path and latency. This description can be used in similar structures of other hash algorithms, such as SHA-1, SHA-2 and RIPEMD-160, which have comparable data dependence. The proposed MD5 hardware architecture achieves a high throughput/area ratio, results of implementation in an FPGA are presented and discussed, as well as comparisons against related works.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e91-d.10.2519/_p
Copier
@ARTICLE{e91-d_10_2519,
author={Ignacio ALGREDO-BADILLO, Claudia FEREGRINO-URIBE, Rene CUMPLIDO, Miguel MORALES-SANDOVAL, },
journal={IEICE TRANSACTIONS on Information},
title={Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description},
year={2008},
volume={E91-D},
number={10},
pages={2519-2523},
abstract={MD5 is a cryptographic algorithm used for authentication. When implemented in hardware, the performance is affected by the data dependency of the iterative compression function. In this paper, a new functional description is proposed with the aim of achieving higher throughput by mean of reducing the critical path and latency. This description can be used in similar structures of other hash algorithms, such as SHA-1, SHA-2 and RIPEMD-160, which have comparable data dependence. The proposed MD5 hardware architecture achieves a high throughput/area ratio, results of implementation in an FPGA are presented and discussed, as well as comparisons against related works.},
keywords={},
doi={10.1093/ietisy/e91-d.10.2519},
ISSN={1745-1361},
month={October},}
Copier
TY - JOUR
TI - Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description
T2 - IEICE TRANSACTIONS on Information
SP - 2519
EP - 2523
AU - Ignacio ALGREDO-BADILLO
AU - Claudia FEREGRINO-URIBE
AU - Rene CUMPLIDO
AU - Miguel MORALES-SANDOVAL
PY - 2008
DO - 10.1093/ietisy/e91-d.10.2519
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E91-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2008
AB - MD5 is a cryptographic algorithm used for authentication. When implemented in hardware, the performance is affected by the data dependency of the iterative compression function. In this paper, a new functional description is proposed with the aim of achieving higher throughput by mean of reducing the critical path and latency. This description can be used in similar structures of other hash algorithms, such as SHA-1, SHA-2 and RIPEMD-160, which have comparable data dependence. The proposed MD5 hardware architecture achieves a high throughput/area ratio, results of implementation in an FPGA are presented and discussed, as well as comparisons against related works.
ER -