The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
L'architecture cascode NMOS a été testée par le modèle du corps humain (HBM), le modèle de machine (MM) et le générateur d'impulsions de ligne de transmission (TLP) dans cet article. Pour le TLP, les données détaillées sur le silicium ont été bien analysées dans de nombreux paramètres, tels que la première tension de déclenchement (Vt1), le premier courant de déclenchement (It1), la tension de maintien (Vh) et la courbe TLP IV. Outre les trois types d'événements de décharge électrostatique (ESD) ci-dessus, la tension de claquage de l'oxyde de grille du dispositif est également prise en compte et les corrélations entre HBM, MM et TLP sont également observées. Afin d'expliquer les mécanismes d'activation des transistors bipolaires, deux types de modèles ont été proposés dans cet article. Dans les cas typiques, la résistance du substrat diminue à mesure que la technologie progresse. D'une part, pour les processus plus anciens que le processus 0.35 µm, tels que 0.5 µm et 1 µm, les concepteurs ESD peuvent utiliser des insertions de détection pour déclencher l'activation uniforme des circuits intégrés (CI). Le modèle latéral NPN peut dominer les performances ESD dans des processus aussi anciens. D'autre part, dans les processus de 0.18 µm et plus récents, tels que 0.15 µm, 0.13 µm, 90 nm, etc., les concepteurs ESD doivent utiliser des structures d'insertion sans captage. Le modèle central NPN peut dominer les performances ESD dans de tels processus. Après avoir combiné les deux modèles, les mécanismes d'activation bipolaires peuvent être expliqués par "les courants ESD se produisent des régions latérales vers les régions centrales". Outre les problèmes d'activation des transistors bipolaires parasites ESD, une autre raison pour laquelle les concepteurs ESD devraient utiliser des insertions sans détection dans les processus submicroniques profonds est la diminution de la tension de claquage de l'oxyde de grille. À mesure que la taille du circuit intégré diminue, l’épaisseur de l’oxyde de grille diminue. L’épaisseur plus fine de l’oxyde de grille rencontrera une tension de claquage de l’oxyde de grille plus petite. Afin d'éviter d'endommager l'oxyde de grille sous des contraintes ESD, les concepteurs ESD doivent s'efforcer de diminuer les résistances d'activation des dispositifs ESD. Les dispositifs de protection ESD avec de faibles résistances d'activation peuvent supporter des courants plus importants pour la même tension TLP. Dans cet article, les données sur le silicium montrent que la résistance d'activation du transistor cascode NMOS à insertion sans capteur est inférieure à la résistance d'activation du transistor NMOS cascode à insertion de capteur. Bien que cet article découvre des mécanismes d'activation NPN basés sur la structure cascode NMOS, les concepteurs ESD peuvent adopter les mêmes théories pour d'autres types de structures de protection ESD, telles qu'un seul transistor NMOS poly Gate-Grounded (GGNMOST). Les concepteurs ESD peuvent utiliser une architecture d'insertion à capteur pour les transistors NMOS dans les processus bas de gamme, mais utilisent l'architecture d'insertion sans capteur pour GGNMOST dans les processus haut de gamme. Ils peuvent alors obtenir les performances ESD optimisées.
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Shao-Chang HUANG, Ke-Horng CHEN, "Substrate Pick-Up Impacting on ESD Performances of Cascode NMOS Transistors" in IEICE TRANSACTIONS on Fundamentals,
vol. E94-A, no. 2, pp. 688-695, February 2011, doi: 10.1587/transfun.E94.A.688.
Abstract: The cascode NMOS architecture has been tested by the Human Body Model (HBM), Machine Model (MM) and Transmission Line Pulse Generator (TLP) in this paper. For the TLP, detailed silicon data have been analyzed well in many parameters, such as the first triggering-on voltage (Vt1), the first triggering-on current (It1), the holding voltage (Vh), and the TLP I-V curve. Besides the above three kinds of Electrostatic Discharge (ESD) events, the device gate oxide breakdown voltage is also taken into consideration and the correlations between HBM, MM and TLP are also observed. In order to explain the bipolar transistor turning-on mechanisms, two kinds of models have been proposed in this paper. In typical cases, substrate resistance decreases as the technology advances. On the one hand, for processes older than the 0.35 µm process, such as 0.5 µm and 1 µm, ESD designers can use pick-up insertions to trigger integrated circuits (IC) turn on uniformly. The NPN Side Model can dominate ESD performances in such old processes. On the other hand, in 0.18 µm and newer processes, such as 0.15 µm, 0.13 µm, 90 nm, etc., ESD designers must use non-pick-up insertion structures. The NPN Central Model can dominate ESD performances in such processes. After combining both models together, the bipolar turning-on mechanisms can be explained as "ESD currents occur from side regions to central regions." Besides ESD parasitic bipolar transistor turning-on concerns, another reason that ESD designers should use non-pick-up insertions in deep sub-micron processes is the decreasing of the gate oxide breakdown voltage. As IC size scales down, the gate oxide thickness lessens. The thinner gate oxide thickness will encounter a smaller gate oxide breakdown voltage. In order to avoid gate oxide damage under ESD stresses, ESD designers should endeavor to decrease ESD device turn-on resistances. ESD protecting devices with low turn-on resistances can endure larger currents for the same TLP voltage. In this paper, silicon data show that the non-pick-up insertion cascode NMOS transistor's turning on resistance is smaller than the pick-up insertion cascode NMOS transistor's turning on resistance. Although this paper discovers NPN turning-on mechanisms based on the cascode NMOS structure, ESD designers can adopt the same theories for other kinds of ESD protecting structures, such as one single poly Gate-Grounded NMOS transistor (GGNMOST). ESD designers can use pick-up insertion architecture for NMOS transistors in the low-end processes, but utilize the non-pick-up insertion architecture for GGNMOST in the high-end processes. Then they can obtain the optimized ESD performances.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.688/_p
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@ARTICLE{e94-a_2_688,
author={Shao-Chang HUANG, Ke-Horng CHEN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Substrate Pick-Up Impacting on ESD Performances of Cascode NMOS Transistors},
year={2011},
volume={E94-A},
number={2},
pages={688-695},
abstract={The cascode NMOS architecture has been tested by the Human Body Model (HBM), Machine Model (MM) and Transmission Line Pulse Generator (TLP) in this paper. For the TLP, detailed silicon data have been analyzed well in many parameters, such as the first triggering-on voltage (Vt1), the first triggering-on current (It1), the holding voltage (Vh), and the TLP I-V curve. Besides the above three kinds of Electrostatic Discharge (ESD) events, the device gate oxide breakdown voltage is also taken into consideration and the correlations between HBM, MM and TLP are also observed. In order to explain the bipolar transistor turning-on mechanisms, two kinds of models have been proposed in this paper. In typical cases, substrate resistance decreases as the technology advances. On the one hand, for processes older than the 0.35 µm process, such as 0.5 µm and 1 µm, ESD designers can use pick-up insertions to trigger integrated circuits (IC) turn on uniformly. The NPN Side Model can dominate ESD performances in such old processes. On the other hand, in 0.18 µm and newer processes, such as 0.15 µm, 0.13 µm, 90 nm, etc., ESD designers must use non-pick-up insertion structures. The NPN Central Model can dominate ESD performances in such processes. After combining both models together, the bipolar turning-on mechanisms can be explained as "ESD currents occur from side regions to central regions." Besides ESD parasitic bipolar transistor turning-on concerns, another reason that ESD designers should use non-pick-up insertions in deep sub-micron processes is the decreasing of the gate oxide breakdown voltage. As IC size scales down, the gate oxide thickness lessens. The thinner gate oxide thickness will encounter a smaller gate oxide breakdown voltage. In order to avoid gate oxide damage under ESD stresses, ESD designers should endeavor to decrease ESD device turn-on resistances. ESD protecting devices with low turn-on resistances can endure larger currents for the same TLP voltage. In this paper, silicon data show that the non-pick-up insertion cascode NMOS transistor's turning on resistance is smaller than the pick-up insertion cascode NMOS transistor's turning on resistance. Although this paper discovers NPN turning-on mechanisms based on the cascode NMOS structure, ESD designers can adopt the same theories for other kinds of ESD protecting structures, such as one single poly Gate-Grounded NMOS transistor (GGNMOST). ESD designers can use pick-up insertion architecture for NMOS transistors in the low-end processes, but utilize the non-pick-up insertion architecture for GGNMOST in the high-end processes. Then they can obtain the optimized ESD performances.},
keywords={},
doi={10.1587/transfun.E94.A.688},
ISSN={1745-1337},
month={February},}
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TY - JOUR
TI - Substrate Pick-Up Impacting on ESD Performances of Cascode NMOS Transistors
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 688
EP - 695
AU - Shao-Chang HUANG
AU - Ke-Horng CHEN
PY - 2011
DO - 10.1587/transfun.E94.A.688
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2011
AB - The cascode NMOS architecture has been tested by the Human Body Model (HBM), Machine Model (MM) and Transmission Line Pulse Generator (TLP) in this paper. For the TLP, detailed silicon data have been analyzed well in many parameters, such as the first triggering-on voltage (Vt1), the first triggering-on current (It1), the holding voltage (Vh), and the TLP I-V curve. Besides the above three kinds of Electrostatic Discharge (ESD) events, the device gate oxide breakdown voltage is also taken into consideration and the correlations between HBM, MM and TLP are also observed. In order to explain the bipolar transistor turning-on mechanisms, two kinds of models have been proposed in this paper. In typical cases, substrate resistance decreases as the technology advances. On the one hand, for processes older than the 0.35 µm process, such as 0.5 µm and 1 µm, ESD designers can use pick-up insertions to trigger integrated circuits (IC) turn on uniformly. The NPN Side Model can dominate ESD performances in such old processes. On the other hand, in 0.18 µm and newer processes, such as 0.15 µm, 0.13 µm, 90 nm, etc., ESD designers must use non-pick-up insertion structures. The NPN Central Model can dominate ESD performances in such processes. After combining both models together, the bipolar turning-on mechanisms can be explained as "ESD currents occur from side regions to central regions." Besides ESD parasitic bipolar transistor turning-on concerns, another reason that ESD designers should use non-pick-up insertions in deep sub-micron processes is the decreasing of the gate oxide breakdown voltage. As IC size scales down, the gate oxide thickness lessens. The thinner gate oxide thickness will encounter a smaller gate oxide breakdown voltage. In order to avoid gate oxide damage under ESD stresses, ESD designers should endeavor to decrease ESD device turn-on resistances. ESD protecting devices with low turn-on resistances can endure larger currents for the same TLP voltage. In this paper, silicon data show that the non-pick-up insertion cascode NMOS transistor's turning on resistance is smaller than the pick-up insertion cascode NMOS transistor's turning on resistance. Although this paper discovers NPN turning-on mechanisms based on the cascode NMOS structure, ESD designers can adopt the same theories for other kinds of ESD protecting structures, such as one single poly Gate-Grounded NMOS transistor (GGNMOST). ESD designers can use pick-up insertion architecture for NMOS transistors in the low-end processes, but utilize the non-pick-up insertion architecture for GGNMOST in the high-end processes. Then they can obtain the optimized ESD performances.
ER -