The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article présente une nouvelle procédure de conception dans le domaine temporel pour des amplificateurs à compensation de Miller imbriqués (NMC) à trois étages à stabilisation rapide. Dans la méthodologie de conception proposée, l'amplificateur est conçu pour se stabiliser dans un laps de temps défini avec une précision de stabilisation donnée en optimisant à la fois la consommation d'énergie et la surface de la puce en silicium. Des équations de conception détaillées sont présentées et les résultats de simulation au niveau du circuit sont fournis pour vérifier l'utilité de la procédure de conception proposée par rapport aux schémas de conception rapportés précédemment.
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Mohammad YAVARI, "A Design Procedure for CMOS Three-Stage NMC Amplifiers" in IEICE TRANSACTIONS on Fundamentals,
vol. E94-A, no. 2, pp. 639-645, February 2011, doi: 10.1587/transfun.E94.A.639.
Abstract: This paper presents a novel time-domain design procedure for fast-settling three-stage nested-Miller compensated (NMC) amplifiers. In the proposed design methodology, the amplifier is designed to settle within a definite time period with a given settling accuracy by optimizing both the power consumption and silicon die area. Detailed design equations are presented and the circuit level simulation results are provided to verify the usefulness of the proposed design procedure with respect to the previously reported design schemes.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.639/_p
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@ARTICLE{e94-a_2_639,
author={Mohammad YAVARI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Design Procedure for CMOS Three-Stage NMC Amplifiers},
year={2011},
volume={E94-A},
number={2},
pages={639-645},
abstract={This paper presents a novel time-domain design procedure for fast-settling three-stage nested-Miller compensated (NMC) amplifiers. In the proposed design methodology, the amplifier is designed to settle within a definite time period with a given settling accuracy by optimizing both the power consumption and silicon die area. Detailed design equations are presented and the circuit level simulation results are provided to verify the usefulness of the proposed design procedure with respect to the previously reported design schemes.},
keywords={},
doi={10.1587/transfun.E94.A.639},
ISSN={1745-1337},
month={February},}
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TY - JOUR
TI - A Design Procedure for CMOS Three-Stage NMC Amplifiers
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 639
EP - 645
AU - Mohammad YAVARI
PY - 2011
DO - 10.1587/transfun.E94.A.639
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2011
AB - This paper presents a novel time-domain design procedure for fast-settling three-stage nested-Miller compensated (NMC) amplifiers. In the proposed design methodology, the amplifier is designed to settle within a definite time period with a given settling accuracy by optimizing both the power consumption and silicon die area. Detailed design equations are presented and the circuit level simulation results are provided to verify the usefulness of the proposed design procedure with respect to the previously reported design schemes.
ER -