The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article décrit une méthode de traitement d'exponentiation modulaire et une architecture de circuit pouvant présenter les performances maximales des ressources FPGA. L'architecture d'exponentiation modulaire que nous proposons comprend trois techniques principales. La première consiste à améliorer l'algorithme de multiplication de Montgomery afin de maximiser les performances de l'unité de multiplication dans un FPGA. La seconde consiste à équilibrer et à améliorer le retard du circuit. Le troisième est d’assurer l’évolutivité du circuit. Notre architecture peut effectuer des opérations rapides en utilisant des ressources à petite échelle ; en particulier, il peut réaliser une exponentiation modulaire de 512 bits en 0.26 ms seulement avec le plus petit FPGA Virtex-4, XC4VF12-10SF363. En fait, le nombre de SLICE utilisées est d'env. 4200, ce qui prouve la compacité de notre conception. De plus, l'évolutivité de notre conception permet également de traiter des exponentiations modulaires de 1024 1536, 2048 XNUMX et XNUMX XNUMX bits dans le même circuit.
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Daisuke SUZUKI, Tsutomu MATSUMOTO, "How to Maximize the Potential of FPGA-Based DSPs for Modular Exponentiation" in IEICE TRANSACTIONS on Fundamentals,
vol. E94-A, no. 1, pp. 211-222, January 2011, doi: 10.1587/transfun.E94.A.211.
Abstract: This paper describes a modular exponentiation processing method and circuit architecture that can exhibit the maximum performance of FPGA resources. The modular exponentiation architecture proposed by us comprises three main techniques. The first one is to improve the Montgomery multiplication algorithm in order to maximize the performance of the multiplication unit in an FPGA. The second one is to balance and improve the circuit delay. The third one is to ensure scalability of the circuit. Our architecture can perform fast operations using small-scale resources; in particular, it can complete a 512-bit modular exponentiation as fast as in 0.26 ms with the smallest Virtex-4 FPGA, XC4VF12-10SF363. In fact the number of SLICEs used is approx. 4200, which proves the compactness of our design. Moreover, the scalability of our design also allows 1024-, 1536-, and 2048-bit modular exponentiations to be processed in the same circuit.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.211/_p
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@ARTICLE{e94-a_1_211,
author={Daisuke SUZUKI, Tsutomu MATSUMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={How to Maximize the Potential of FPGA-Based DSPs for Modular Exponentiation},
year={2011},
volume={E94-A},
number={1},
pages={211-222},
abstract={This paper describes a modular exponentiation processing method and circuit architecture that can exhibit the maximum performance of FPGA resources. The modular exponentiation architecture proposed by us comprises three main techniques. The first one is to improve the Montgomery multiplication algorithm in order to maximize the performance of the multiplication unit in an FPGA. The second one is to balance and improve the circuit delay. The third one is to ensure scalability of the circuit. Our architecture can perform fast operations using small-scale resources; in particular, it can complete a 512-bit modular exponentiation as fast as in 0.26 ms with the smallest Virtex-4 FPGA, XC4VF12-10SF363. In fact the number of SLICEs used is approx. 4200, which proves the compactness of our design. Moreover, the scalability of our design also allows 1024-, 1536-, and 2048-bit modular exponentiations to be processed in the same circuit.},
keywords={},
doi={10.1587/transfun.E94.A.211},
ISSN={1745-1337},
month={January},}
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TY - JOUR
TI - How to Maximize the Potential of FPGA-Based DSPs for Modular Exponentiation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 211
EP - 222
AU - Daisuke SUZUKI
AU - Tsutomu MATSUMOTO
PY - 2011
DO - 10.1587/transfun.E94.A.211
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2011
AB - This paper describes a modular exponentiation processing method and circuit architecture that can exhibit the maximum performance of FPGA resources. The modular exponentiation architecture proposed by us comprises three main techniques. The first one is to improve the Montgomery multiplication algorithm in order to maximize the performance of the multiplication unit in an FPGA. The second one is to balance and improve the circuit delay. The third one is to ensure scalability of the circuit. Our architecture can perform fast operations using small-scale resources; in particular, it can complete a 512-bit modular exponentiation as fast as in 0.26 ms with the smallest Virtex-4 FPGA, XC4VF12-10SF363. In fact the number of SLICEs used is approx. 4200, which proves the compactness of our design. Moreover, the scalability of our design also allows 1024-, 1536-, and 2048-bit modular exponentiations to be processed in the same circuit.
ER -