The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
À l’ère du submicronique profond, le retard des câbles devient un goulot d’étranglement tout en poursuivant une vitesse d’horloge système encore plus élevée. Plusieurs architectures de registres distribués (DR) ont été proposées pour résoudre ce problème en gardant la plupart des fils locaux. Dans cet article, nous proposons un nouvel algorithme de synthèse de communication à ressources limitées pour optimiser à la fois les connexions inter-îles (IIC) et le ciblage de la latence sur la microarchitecture de fichiers de registres distribués (DRFM). Les résultats expérimentaux montrent que jusqu'à 24.7 % et 12.7 % de réduction de l'IIC et de la latence peuvent être obtenus respectivement par rapport aux travaux précédents.
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Juinn-Dar HUANG, Chia-I CHEN, Yen-Ting LIN, Wan-Ling HSU, "Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture" in IEICE TRANSACTIONS on Fundamentals,
vol. E94-A, no. 4, pp. 1151-1155, April 2011, doi: 10.1587/transfun.E94.A.1151.
Abstract: In deep-submicron era, wire delay is becoming a bottleneck while pursuing even higher system clock speed. Several distributed register (DR) architectures have been proposed to cope with this problem by keeping most wires local. In this article, we propose a new resource-constrained communication synthesis algorithm for optimizing both inter-island connections (IICs) and latency targeting on distributed register-file microarchitecture (DRFM). The experimental results show that up to 24.7% and 12.7% reduction on IIC and latency can be achieved respectively as compared to the previous work.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.1151/_p
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@ARTICLE{e94-a_4_1151,
author={Juinn-Dar HUANG, Chia-I CHEN, Yen-Ting LIN, Wan-Ling HSU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture},
year={2011},
volume={E94-A},
number={4},
pages={1151-1155},
abstract={In deep-submicron era, wire delay is becoming a bottleneck while pursuing even higher system clock speed. Several distributed register (DR) architectures have been proposed to cope with this problem by keeping most wires local. In this article, we propose a new resource-constrained communication synthesis algorithm for optimizing both inter-island connections (IICs) and latency targeting on distributed register-file microarchitecture (DRFM). The experimental results show that up to 24.7% and 12.7% reduction on IIC and latency can be achieved respectively as compared to the previous work.},
keywords={},
doi={10.1587/transfun.E94.A.1151},
ISSN={1745-1337},
month={April},}
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TY - JOUR
TI - Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1151
EP - 1155
AU - Juinn-Dar HUANG
AU - Chia-I CHEN
AU - Yen-Ting LIN
AU - Wan-Ling HSU
PY - 2011
DO - 10.1587/transfun.E94.A.1151
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2011
AB - In deep-submicron era, wire delay is becoming a bottleneck while pursuing even higher system clock speed. Several distributed register (DR) architectures have been proposed to cope with this problem by keeping most wires local. In this article, we propose a new resource-constrained communication synthesis algorithm for optimizing both inter-island connections (IICs) and latency targeting on distributed register-file microarchitecture (DRFM). The experimental results show that up to 24.7% and 12.7% reduction on IIC and latency can be achieved respectively as compared to the previous work.
ER -