The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Une technique de modélisation basée sur les langages de description matérielle (HDL) pour les circuits asynchrones est présentée dans cet article. Un package de prise de contact HDL a été développé pour exprimer des systèmes numériques de type poignée de main en VHDL et Verilog. Des circuits en mode rafale et en mode rafale étendu (BM/XBM) ont été utilisés pour démontrer l’utilité de ce travail. Cette recherche a permis de prototyper avec succès des comparateurs, des additionneurs, un encodeur/décodeur RSA et plusieurs circuits auto-temporisés pour les conceptions de circuits intégrés et de FPGA entièrement personnalisés. De plus, le package de prise de contact HDL mis en œuvre par cette recherche peut être utilisé pour développer des bancs de tests comportementaux pour étudier et analyser des conceptions asynchrones. L'extraction d'informations de synchronisation détaillées à partir de machines à états finis asynchrones (AFSM), la détection de défauts de retard pour les modules fonctionnels synthétisés à temporisation automatique et la localisation de violations de mode fondamental dans les AFSM réalisés sont des applications éprouvées. La technique de modélisation HDL anticipée et la procédure de transformation sont détaillées dans la suite de cet article.
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Jung-Lin YANG, Jau-Cheng WEI, Shin-Nung LU, "HDLs Modeling Technique for Burst-Mode and Extended Burst-Mode Asynchronous Circuits" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 12, pp. 2590-2599, December 2010, doi: 10.1587/transfun.E93.A.2590.
Abstract: A hardware description languages (HDLs) based modeling technique for asynchronous circuits is presented in this paper. A HDLs handshake package has been developed for expressing handshake-style digital systems in both VHDL and Verilog. Burst-mode and extended burst-mode (BM/XBM) circuits were used to demonstrate the usefulness of this work. This research successfully prototyped comparators, adders, RSA encoder/decoder, and several self-timed circuits for the full-custom IC and FPGAs designs. Furthermore, the HDLs handshake package implemented by this research can be utilized to develop behavioral test benches for studying and analyzing asynchronous designs. Extracting detailed timing information from asynchronous finite state machines (AFSMs), detecting delay faults for synthesized self-timed functional modules, and locating fundamental mode violation within realized AFSMs are proven applications. The anticipated HDL modeling technique and the transformation procedure are detailed in the rest of this paper.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.2590/_p
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@ARTICLE{e93-a_12_2590,
author={Jung-Lin YANG, Jau-Cheng WEI, Shin-Nung LU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={HDLs Modeling Technique for Burst-Mode and Extended Burst-Mode Asynchronous Circuits},
year={2010},
volume={E93-A},
number={12},
pages={2590-2599},
abstract={A hardware description languages (HDLs) based modeling technique for asynchronous circuits is presented in this paper. A HDLs handshake package has been developed for expressing handshake-style digital systems in both VHDL and Verilog. Burst-mode and extended burst-mode (BM/XBM) circuits were used to demonstrate the usefulness of this work. This research successfully prototyped comparators, adders, RSA encoder/decoder, and several self-timed circuits for the full-custom IC and FPGAs designs. Furthermore, the HDLs handshake package implemented by this research can be utilized to develop behavioral test benches for studying and analyzing asynchronous designs. Extracting detailed timing information from asynchronous finite state machines (AFSMs), detecting delay faults for synthesized self-timed functional modules, and locating fundamental mode violation within realized AFSMs are proven applications. The anticipated HDL modeling technique and the transformation procedure are detailed in the rest of this paper.},
keywords={},
doi={10.1587/transfun.E93.A.2590},
ISSN={1745-1337},
month={December},}
Copier
TY - JOUR
TI - HDLs Modeling Technique for Burst-Mode and Extended Burst-Mode Asynchronous Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2590
EP - 2599
AU - Jung-Lin YANG
AU - Jau-Cheng WEI
AU - Shin-Nung LU
PY - 2010
DO - 10.1587/transfun.E93.A.2590
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2010
AB - A hardware description languages (HDLs) based modeling technique for asynchronous circuits is presented in this paper. A HDLs handshake package has been developed for expressing handshake-style digital systems in both VHDL and Verilog. Burst-mode and extended burst-mode (BM/XBM) circuits were used to demonstrate the usefulness of this work. This research successfully prototyped comparators, adders, RSA encoder/decoder, and several self-timed circuits for the full-custom IC and FPGAs designs. Furthermore, the HDLs handshake package implemented by this research can be utilized to develop behavioral test benches for studying and analyzing asynchronous designs. Extracting detailed timing information from asynchronous finite state machines (AFSMs), detecting delay faults for synthesized self-timed functional modules, and locating fundamental mode violation within realized AFSMs are proven applications. The anticipated HDL modeling technique and the transformation procedure are detailed in the rest of this paper.
ER -