The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article propose un processeur économe en énergie qui peut être utilisé comme alternative de conception aux processeurs à mise à l'échelle dynamique de tension (DVS) dans la conception de systèmes embarqués. Le processeur se compose de plusieurs cœurs PE (élément de traitement) et d'une mémoire cache sélective associative. Les cœurs PE ont la même architecture de jeu d’instructions mais diffèrent par leurs vitesses d’horloge et leur consommation d’énergie. Un seul cœur PE est activé à la fois et les autres cœurs PE sont désactivés à l'aide de techniques de déclenchement d'horloge et de déclenchement de signal. Le principal avantage par rapport aux processeurs DVS est une légère surcharge liée à la modification de ses performances. La simulation au niveau de la porte démontre que notre processeur peut modifier ses performances en 1.5 microsecondes et dissiper environ 10 nanojoules, alors que les processeurs DVS conventionnels ont besoin de centaines de microsecondes et dissipent quelques microjoules pour la transition des performances. Cela permet d'appliquer notre processeur multi-performances à de nombreux systèmes en temps réel et d'effectuer un contrôle de tension dynamique plus fin et plus sophistiqué.
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Tohru ISHIHARA, "A Multi-Performance Processor for Reducing the Energy Consumption of Real-Time Embedded Systems" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 12, pp. 2533-2541, December 2010, doi: 10.1587/transfun.E93.A.2533.
Abstract: This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The processor consists of multiple PE (processing element) cores and a selective set-associative cache memory. The PE-cores have the same instruction set architecture but differ in their clock speeds and energy consumptions. Only a single PE-core is activated at a time and the other PE-cores are deactivated using clock gating and signal gating techniques. The major advantage over the DVS processors is a small overhead for changing its performance. The gate-level simulation demonstrates that our processor can change its performance within 1.5 microsecond and dissipates about 10 nano-joule while conventional DVS processors need hundreds of microseconds and dissipate a few micro-joule for the performance transition. This makes it possible to apply our multi-performance processor to many real-time systems and to perform finer grained and more sophisticated dynamic voltage control.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.2533/_p
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@ARTICLE{e93-a_12_2533,
author={Tohru ISHIHARA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Multi-Performance Processor for Reducing the Energy Consumption of Real-Time Embedded Systems},
year={2010},
volume={E93-A},
number={12},
pages={2533-2541},
abstract={This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The processor consists of multiple PE (processing element) cores and a selective set-associative cache memory. The PE-cores have the same instruction set architecture but differ in their clock speeds and energy consumptions. Only a single PE-core is activated at a time and the other PE-cores are deactivated using clock gating and signal gating techniques. The major advantage over the DVS processors is a small overhead for changing its performance. The gate-level simulation demonstrates that our processor can change its performance within 1.5 microsecond and dissipates about 10 nano-joule while conventional DVS processors need hundreds of microseconds and dissipate a few micro-joule for the performance transition. This makes it possible to apply our multi-performance processor to many real-time systems and to perform finer grained and more sophisticated dynamic voltage control.},
keywords={},
doi={10.1587/transfun.E93.A.2533},
ISSN={1745-1337},
month={December},}
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TY - JOUR
TI - A Multi-Performance Processor for Reducing the Energy Consumption of Real-Time Embedded Systems
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2533
EP - 2541
AU - Tohru ISHIHARA
PY - 2010
DO - 10.1587/transfun.E93.A.2533
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2010
AB - This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The processor consists of multiple PE (processing element) cores and a selective set-associative cache memory. The PE-cores have the same instruction set architecture but differ in their clock speeds and energy consumptions. Only a single PE-core is activated at a time and the other PE-cores are deactivated using clock gating and signal gating techniques. The major advantage over the DVS processors is a small overhead for changing its performance. The gate-level simulation demonstrates that our processor can change its performance within 1.5 microsecond and dissipates about 10 nano-joule while conventional DVS processors need hundreds of microseconds and dissipate a few micro-joule for the performance transition. This makes it possible to apply our multi-performance processor to many real-time systems and to perform finer grained and more sophisticated dynamic voltage control.
ER -