The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
L'estimation de mouvement de taille de bloc variable développée par la dernière norme de codage vidéo H.264/AVC constitue l'approche efficace pour réduire les redondances temporelles. La complexité informatique intensive provenant de la technique de taille de bloc variable rend l’accélérateur câblé essentiel pour les applications en temps réel. Propager des sommes partielles de différences absolues (Propager un SAD partiel) et Arbre TRISTE les moteurs câblés surpassent les autres homologues, en particulier compte tenu de l'impact de la prise en charge de la technique de taille de bloc variable. Dans cet article, les auteurs appliquent les approches au niveau de l'architecture et au niveau du circuit pour améliorer la fréquence de fonctionnement maximale et réduire la surcharge matérielle de Propager un SAD partiel et Arbre TRISTE, tandis que d'autres mesures, en termes de latence, de bande passante mémoire et d'utilisation du matériel, des architectures d'origine sont conservées. Les expériences démontrent qu'en utilisant les approches proposées, à une fréquence de fonctionnement de 110.8 MHz, par rapport aux architectures originales, 14.7 % et 18.0 % du nombre de portes peuvent être économisés pour Propager un SAD partiel et Arbre TRISTE, respectivement. Avec la technologie CMOS TSMC 0.18 µm 1P6M, le projet proposé Propager un SAD partiel L'architecture atteint une fréquence de fonctionnement de 231.6 MHz pour un coût de 84.1 k portes. En conséquence, la fréquence de travail maximale de l'optimisé Arbre TRISTE L'architecture est améliorée à 204.8 MHz, soit presque deux fois celle d'origine, tandis que sa surcharge matérielle n'est que de 88.5 k-gate.
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Zhenyu LIU, Dongsheng WANG, Takeshi IKENAGA, "Architecture and Circuit Optimization of Hardwired Integer Motion Estimation Engine for H.264/AVC" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 11, pp. 2065-2073, November 2010, doi: 10.1587/transfun.E93.A.2065.
Abstract: Variable block size motion estimation developed by the latest video coding standard H.264/AVC is the efficient approach to reduce the temporal redundancies. The intensive computational complexity coming from the variable block size technique makes the hardwired accelerator essential, for real-time applications. Propagate partial sums of absolute differences (Propagate Partial SAD) and SAD Tree hardwired engines outperform other counterparts, especially considering the impact of supporting variable block size technique. In this paper, the authors apply the architecture-level and the circuit-level approaches to improve the maximum operating frequency and reduce the hardware overhead of Propagate Partial SAD and SAD Tree, while other metrics, in terms of latency, memory bandwidth and hardware utilization, of the original architectures are maintained. Experiments demonstrate that by using the proposed approaches, at 110.8 MHz operating frequency, compared with the original architectures, 14.7% and 18.0% gate count can be saved for Propagate Partial SAD and SAD Tree, respectively. With TSMC 0.18 µm 1P6M CMOS technology, the proposed Propagate Partial SAD architecture achieves 231.6 MHz operating frequency at a cost of 84.1 k gates. Correspondingly, the maximum work frequency of the optimized SAD Tree architecture is improved to 204.8 MHz, which is almost two times of the original one, while its hardware overhead is merely 88.5 k-gate.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.2065/_p
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@ARTICLE{e93-a_11_2065,
author={Zhenyu LIU, Dongsheng WANG, Takeshi IKENAGA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Architecture and Circuit Optimization of Hardwired Integer Motion Estimation Engine for H.264/AVC},
year={2010},
volume={E93-A},
number={11},
pages={2065-2073},
abstract={Variable block size motion estimation developed by the latest video coding standard H.264/AVC is the efficient approach to reduce the temporal redundancies. The intensive computational complexity coming from the variable block size technique makes the hardwired accelerator essential, for real-time applications. Propagate partial sums of absolute differences (Propagate Partial SAD) and SAD Tree hardwired engines outperform other counterparts, especially considering the impact of supporting variable block size technique. In this paper, the authors apply the architecture-level and the circuit-level approaches to improve the maximum operating frequency and reduce the hardware overhead of Propagate Partial SAD and SAD Tree, while other metrics, in terms of latency, memory bandwidth and hardware utilization, of the original architectures are maintained. Experiments demonstrate that by using the proposed approaches, at 110.8 MHz operating frequency, compared with the original architectures, 14.7% and 18.0% gate count can be saved for Propagate Partial SAD and SAD Tree, respectively. With TSMC 0.18 µm 1P6M CMOS technology, the proposed Propagate Partial SAD architecture achieves 231.6 MHz operating frequency at a cost of 84.1 k gates. Correspondingly, the maximum work frequency of the optimized SAD Tree architecture is improved to 204.8 MHz, which is almost two times of the original one, while its hardware overhead is merely 88.5 k-gate.},
keywords={},
doi={10.1587/transfun.E93.A.2065},
ISSN={1745-1337},
month={November},}
Copier
TY - JOUR
TI - Architecture and Circuit Optimization of Hardwired Integer Motion Estimation Engine for H.264/AVC
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2065
EP - 2073
AU - Zhenyu LIU
AU - Dongsheng WANG
AU - Takeshi IKENAGA
PY - 2010
DO - 10.1587/transfun.E93.A.2065
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2010
AB - Variable block size motion estimation developed by the latest video coding standard H.264/AVC is the efficient approach to reduce the temporal redundancies. The intensive computational complexity coming from the variable block size technique makes the hardwired accelerator essential, for real-time applications. Propagate partial sums of absolute differences (Propagate Partial SAD) and SAD Tree hardwired engines outperform other counterparts, especially considering the impact of supporting variable block size technique. In this paper, the authors apply the architecture-level and the circuit-level approaches to improve the maximum operating frequency and reduce the hardware overhead of Propagate Partial SAD and SAD Tree, while other metrics, in terms of latency, memory bandwidth and hardware utilization, of the original architectures are maintained. Experiments demonstrate that by using the proposed approaches, at 110.8 MHz operating frequency, compared with the original architectures, 14.7% and 18.0% gate count can be saved for Propagate Partial SAD and SAD Tree, respectively. With TSMC 0.18 µm 1P6M CMOS technology, the proposed Propagate Partial SAD architecture achieves 231.6 MHz operating frequency at a cost of 84.1 k gates. Correspondingly, the maximum work frequency of the optimized SAD Tree architecture is improved to 204.8 MHz, which is almost two times of the original one, while its hardware overhead is merely 88.5 k-gate.
ER -