The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article aborde le problème de l'optimisation des modèles de métallisation des connexions back-end pour le pilote basé sur un MOSFET de puissance, car les connexions back-end ont tendance à dominer la résistance à l'état passant. Ron du conducteur. Nous proposons un algorithme heuristique pour rechercher de meilleures formes géométriques pour les motifs visant à minimiser Ron et à équilibrer la répartition actuelle. Afin d'accélérer l'analyse, le réseau de résistance équivalent du pilote est modifié en insérant des commutateurs idéaux pour éviter d'inverser à plusieurs reprises la matrice d'admittance. Avec le modèle comportemental du commutateur idéal, nous pouvons accélérer considérablement l’optimisation. La simulation sur trois pilotes issus de données industrielles TEG démontre que notre algorithme peut réduire Ron efficacement en façonnant les métaux de manière appropriée dans une zone de routage donnée.
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Bo YANG, Shigetoshi NAKATAKE, "Fast Shape Optimization of Metalization Patterns for Power-MOSFET Based Driver" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 12, pp. 3052-3060, December 2009, doi: 10.1587/transfun.E92.A.3052.
Abstract: This paper addresses the problem of optimizing metalization patterns of back-end connections for the power-MOSFET based driver since the back-end connections tend to dominate the on-resistance Ron of the driver. We propose a heuristic algorithm to seek for better geometric shapes for the patterns targeting at minimizing Ron and at balancing the current distribution. In order to speed up the analysis, the equivalent resistance network of the driver is modified by inserting ideal switches to avoid repeatedly inverting the admittance matrix. With the behavioral model of the ideal switch, we can significantly accelerate the optimization. Simulation on three drivers from industrial TEG data demonstrates that our algorithm can reduce Ron effectively by shaping metals appropriately within a given routing area.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.3052/_p
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@ARTICLE{e92-a_12_3052,
author={Bo YANG, Shigetoshi NAKATAKE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Fast Shape Optimization of Metalization Patterns for Power-MOSFET Based Driver},
year={2009},
volume={E92-A},
number={12},
pages={3052-3060},
abstract={This paper addresses the problem of optimizing metalization patterns of back-end connections for the power-MOSFET based driver since the back-end connections tend to dominate the on-resistance Ron of the driver. We propose a heuristic algorithm to seek for better geometric shapes for the patterns targeting at minimizing Ron and at balancing the current distribution. In order to speed up the analysis, the equivalent resistance network of the driver is modified by inserting ideal switches to avoid repeatedly inverting the admittance matrix. With the behavioral model of the ideal switch, we can significantly accelerate the optimization. Simulation on three drivers from industrial TEG data demonstrates that our algorithm can reduce Ron effectively by shaping metals appropriately within a given routing area.},
keywords={},
doi={10.1587/transfun.E92.A.3052},
ISSN={1745-1337},
month={December},}
Copier
TY - JOUR
TI - Fast Shape Optimization of Metalization Patterns for Power-MOSFET Based Driver
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3052
EP - 3060
AU - Bo YANG
AU - Shigetoshi NAKATAKE
PY - 2009
DO - 10.1587/transfun.E92.A.3052
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2009
AB - This paper addresses the problem of optimizing metalization patterns of back-end connections for the power-MOSFET based driver since the back-end connections tend to dominate the on-resistance Ron of the driver. We propose a heuristic algorithm to seek for better geometric shapes for the patterns targeting at minimizing Ron and at balancing the current distribution. In order to speed up the analysis, the equivalent resistance network of the driver is modified by inserting ideal switches to avoid repeatedly inverting the admittance matrix. With the behavioral model of the ideal switch, we can significantly accelerate the optimization. Simulation on three drivers from industrial TEG data demonstrates that our algorithm can reduce Ron effectively by shaping metals appropriately within a given routing area.
ER -