The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dans cet article, nous présentons un décodeur de profil principal VC-1 hautes performances pour les applications vidéo haute définition (HD), capable de décoder les flux vidéo HD 720p à 30 ips à 80 MHz. Nous avons implémenté le décodeur avec un processus CMOS un poly huit métaux de 0.13 µm, qui contient environ 261,900 13.9 portes logiques et des mémoires sur puce de 13.1 Ko de SRAM et 5.1 Ko de ROM et occupe une superficie d'environ XNUMX mm.2. Lors de la conception du décodeur VC-1, nous avons utilisé un flux de conception SoC basé sur un modèle, avec lequel nous avons effectué l'exploration de l'espace de conception du décodeur en essayant diverses configurations de canaux de communication. De plus, nous décrivons également des architectures de blocs de calcul optimisées pour satisfaire les exigences des applications VC-1 HD.
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Jinhyun CHO, Doowon LEE, Sangyong YOON, Sanggyu PARK, Soo-Ik CHAE, "VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 1, pp. 279-290, January 2009, doi: 10.1587/transfun.E92.A.279.
Abstract: In this paper, we present a high-performance VC-1 main-profile decoder for high-definition (HD) video applications, which can decode HD 720p video streams with 30 fps at 80 MHz. We implemented the decoder with a one-poly eight-metal 0.13 µm CMOS process, which contains about 261,900 logic gates and on-chip memories of 13.9 KB SRAM and 13.1 KB ROM and occupies an area of about 5.1 mm2. In designing the VC-1 decoder, we used a template-based SoC design flow, with which we performed the design space exploration of the decoder by trying various configurations of communication channels. Moreover, we also describe architectures of the computation blocks optimized to satisfy the requirements of VC-1 HD applications.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.279/_p
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@ARTICLE{e92-a_1_279,
author={Jinhyun CHO, Doowon LEE, Sangyong YOON, Sanggyu PARK, Soo-Ik CHAE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications},
year={2009},
volume={E92-A},
number={1},
pages={279-290},
abstract={In this paper, we present a high-performance VC-1 main-profile decoder for high-definition (HD) video applications, which can decode HD 720p video streams with 30 fps at 80 MHz. We implemented the decoder with a one-poly eight-metal 0.13 µm CMOS process, which contains about 261,900 logic gates and on-chip memories of 13.9 KB SRAM and 13.1 KB ROM and occupies an area of about 5.1 mm2. In designing the VC-1 decoder, we used a template-based SoC design flow, with which we performed the design space exploration of the decoder by trying various configurations of communication channels. Moreover, we also describe architectures of the computation blocks optimized to satisfy the requirements of VC-1 HD applications.},
keywords={},
doi={10.1587/transfun.E92.A.279},
ISSN={1745-1337},
month={January},}
Copier
TY - JOUR
TI - VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 279
EP - 290
AU - Jinhyun CHO
AU - Doowon LEE
AU - Sangyong YOON
AU - Sanggyu PARK
AU - Soo-Ik CHAE
PY - 2009
DO - 10.1587/transfun.E92.A.279
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2009
AB - In this paper, we present a high-performance VC-1 main-profile decoder for high-definition (HD) video applications, which can decode HD 720p video streams with 30 fps at 80 MHz. We implemented the decoder with a one-poly eight-metal 0.13 µm CMOS process, which contains about 261,900 logic gates and on-chip memories of 13.9 KB SRAM and 13.1 KB ROM and occupies an area of about 5.1 mm2. In designing the VC-1 decoder, we used a template-based SoC design flow, with which we performed the design space exploration of the decoder by trying various configurations of communication channels. Moreover, we also describe architectures of the computation blocks optimized to satisfy the requirements of VC-1 HD applications.
ER -