The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dans les conceptions submicroniques profondes, la prévision des retards de porte avec la charge d'interconnexion est un travail remarquable pour l'analyse de synchronisation statique (STA). La capacité efficace Ceff Le concept et le modèle Thevenin qui remplace la grille par une résistance linéaire et une source de tension sont généralement utilisés pour calculer le retard de la grille avec charge d'interconnexion. Dans les méthodes conventionnelles, on ne considère pas que les charges transférées vers la charge d'interconnexion et Ceff dans le modèle de Thévenin ne sont pas égaux. La différence de charge entre la charge d'interconnexion et Ceff a une grande influence sur la précision du calcul Ceff. Dans cet article, un modèle avancé de capacité effective est proposé pour considérer le problème ci-dessus dans le modèle de Thevenin, où l'influence de la différence de charge est modélisée comme une partie de la capacité effective pour calculer le retard de grille. Les résultats expérimentaux montrent une amélioration significative de la précision lorsque la différence de charge entre la charge d'interconnexion et Ceff est considéré.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copier
Minglu JIANG, Zhangcai HUANG, Atsushi KUROKAWA, Shuai FANG, Yasuaki INOUE, "Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 10, pp. 2531-2539, October 2009, doi: 10.1587/transfun.E92.A.2531.
Abstract: In deep submicron designs, predicting gate delays with interconnect load is a noteworthy work for Static Timing Analysis (STA). The effective capacitance Ceff concept and the Thevenin model that replaces the gate with a linear resistor and a voltage source are usually used to calculate the delay of gate with interconnect load. In conventional methods, it is not considered that the charges transferred into interconnect load and Ceff in the Thevenin model are not equal. The charge difference between interconnect load and Ceff has the large influence to the accuracy of computing Ceff. In this paper, an advanced effective capacitance model is proposed to consider the above problem in the Thevenin model, where the influence of the charge difference is modeled as one part of the effective capacitance to compute the gate delay. Experimental results show a significant improvement in accuracy when the charge difference between interconnect load and Ceff is considered.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.2531/_p
Copier
@ARTICLE{e92-a_10_2531,
author={Minglu JIANG, Zhangcai HUANG, Atsushi KUROKAWA, Shuai FANG, Yasuaki INOUE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model},
year={2009},
volume={E92-A},
number={10},
pages={2531-2539},
abstract={In deep submicron designs, predicting gate delays with interconnect load is a noteworthy work for Static Timing Analysis (STA). The effective capacitance Ceff concept and the Thevenin model that replaces the gate with a linear resistor and a voltage source are usually used to calculate the delay of gate with interconnect load. In conventional methods, it is not considered that the charges transferred into interconnect load and Ceff in the Thevenin model are not equal. The charge difference between interconnect load and Ceff has the large influence to the accuracy of computing Ceff. In this paper, an advanced effective capacitance model is proposed to consider the above problem in the Thevenin model, where the influence of the charge difference is modeled as one part of the effective capacitance to compute the gate delay. Experimental results show a significant improvement in accuracy when the charge difference between interconnect load and Ceff is considered.},
keywords={},
doi={10.1587/transfun.E92.A.2531},
ISSN={1745-1337},
month={October},}
Copier
TY - JOUR
TI - Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2531
EP - 2539
AU - Minglu JIANG
AU - Zhangcai HUANG
AU - Atsushi KUROKAWA
AU - Shuai FANG
AU - Yasuaki INOUE
PY - 2009
DO - 10.1587/transfun.E92.A.2531
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 2009
AB - In deep submicron designs, predicting gate delays with interconnect load is a noteworthy work for Static Timing Analysis (STA). The effective capacitance Ceff concept and the Thevenin model that replaces the gate with a linear resistor and a voltage source are usually used to calculate the delay of gate with interconnect load. In conventional methods, it is not considered that the charges transferred into interconnect load and Ceff in the Thevenin model are not equal. The charge difference between interconnect load and Ceff has the large influence to the accuracy of computing Ceff. In this paper, an advanced effective capacitance model is proposed to consider the above problem in the Thevenin model, where the influence of the charge difference is modeled as one part of the effective capacitance to compute the gate delay. Experimental results show a significant improvement in accuracy when the charge difference between interconnect load and Ceff is considered.
ER -