The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dans un système embarqué dans lequel une seule application ou une classe d'applications est exécutée de manière répétée sur un processeur, sa configuration de cache peut être personnalisée de manière à obtenir une configuration optimale. Nous pouvons avoir une configuration de cache optimale qui minimise le temps global d'accès à la mémoire en faisant varier les trois paramètres du cache : le nombre d'ensembles, une taille de ligne et une associativité. Dans cet article, nous proposons d'abord deux algorithmes de simulation de cache : CRCB1 et CRCB2, basés sur Propriété d'inclusion de cache. Ils réalisent une simulation exacte du cache mais réduisent considérablement le nombre de jugements de réussite/échec du cache. Nous proposons en outre trois autres algorithmes d'exploration de l'espace de conception de cache : CRMF1, CRMF2 et CRMF3, basés sur nos observations expérimentales. Ils peuvent trouver une configuration de cache presque optimale du point de vue de temps d'accès. En utilisant notre approche, le nombre de jugements de réussite/échec du cache requis pour optimiser les configurations de cache est réduit à 1/10-1/50 par rapport aux approches conventionnelles. En conséquence, l’approche proposée est en moyenne 3.2 fois plus rapide et au maximum 5.3 fois plus rapide par rapport à l’approche la plus rapide proposée jusqu’à présent. L’approche de simulation de cache proposée permet d’obtenir l’exploration de l’espace de conception de cache la plus rapide au monde en optimisant le temps total d’accès à la mémoire.
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Nobuaki TOJO, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, "An L1 Cache Design Space Exploration System for Embedded Applications" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 6, pp. 1442-1453, June 2009, doi: 10.1587/transfun.E92.A.1442.
Abstract: In an embedded system where a single application or a class of applications is repeatedly executed on a processor, its cache configuration can be customized such that an optimal one is achieved. We can have an optimal cache configuration which minimizes overall memory access time by varying the three cache parameters: the number of sets, a line size, and an associativity. In this paper, we first propose two cache simulation algorithms: CRCB1 and CRCB2, based on Cache Inclusion Property. They realize exact cache simulation but decrease the number of cache hit/miss judgments dramatically. We further propose three more cache design space exploration algorithms: CRMF1, CRMF2, and CRMF3, based on our experimental observations. They can find an almost optimal cache configuration from the viewpoint of access time. By using our approach, the number of cache hit/miss judgments required for optimizing cache configurations is reduced to 1/10-1/50 compared to conventional approaches. As a result, our proposed approach totally runs an average of 3.2 times faster and a maximum of 5.3 times faster compared to the fastest approach proposed so far. Our proposed cache simulation approach achieves the world fastest cache design space exploration when optimizing total memory access time.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.1442/_p
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@ARTICLE{e92-a_6_1442,
author={Nobuaki TOJO, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An L1 Cache Design Space Exploration System for Embedded Applications},
year={2009},
volume={E92-A},
number={6},
pages={1442-1453},
abstract={In an embedded system where a single application or a class of applications is repeatedly executed on a processor, its cache configuration can be customized such that an optimal one is achieved. We can have an optimal cache configuration which minimizes overall memory access time by varying the three cache parameters: the number of sets, a line size, and an associativity. In this paper, we first propose two cache simulation algorithms: CRCB1 and CRCB2, based on Cache Inclusion Property. They realize exact cache simulation but decrease the number of cache hit/miss judgments dramatically. We further propose three more cache design space exploration algorithms: CRMF1, CRMF2, and CRMF3, based on our experimental observations. They can find an almost optimal cache configuration from the viewpoint of access time. By using our approach, the number of cache hit/miss judgments required for optimizing cache configurations is reduced to 1/10-1/50 compared to conventional approaches. As a result, our proposed approach totally runs an average of 3.2 times faster and a maximum of 5.3 times faster compared to the fastest approach proposed so far. Our proposed cache simulation approach achieves the world fastest cache design space exploration when optimizing total memory access time.},
keywords={},
doi={10.1587/transfun.E92.A.1442},
ISSN={1745-1337},
month={June},}
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TY - JOUR
TI - An L1 Cache Design Space Exploration System for Embedded Applications
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1442
EP - 1453
AU - Nobuaki TOJO
AU - Nozomu TOGAWA
AU - Masao YANAGISAWA
AU - Tatsuo OHTSUKI
PY - 2009
DO - 10.1587/transfun.E92.A.1442
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2009
AB - In an embedded system where a single application or a class of applications is repeatedly executed on a processor, its cache configuration can be customized such that an optimal one is achieved. We can have an optimal cache configuration which minimizes overall memory access time by varying the three cache parameters: the number of sets, a line size, and an associativity. In this paper, we first propose two cache simulation algorithms: CRCB1 and CRCB2, based on Cache Inclusion Property. They realize exact cache simulation but decrease the number of cache hit/miss judgments dramatically. We further propose three more cache design space exploration algorithms: CRMF1, CRMF2, and CRMF3, based on our experimental observations. They can find an almost optimal cache configuration from the viewpoint of access time. By using our approach, the number of cache hit/miss judgments required for optimizing cache configurations is reduced to 1/10-1/50 compared to conventional approaches. As a result, our proposed approach totally runs an average of 3.2 times faster and a maximum of 5.3 times faster compared to the fastest approach proposed so far. Our proposed cache simulation approach achieves the world fastest cache design space exploration when optimizing total memory access time.
ER -