The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Un processeur embarqué à faible consommation d'énergie et hautes performances est crucial dans la conception des futurs systèmes embarqués nomades. L'amélioration des accès à la mémoire, en particulier l'amélioration de la localité spatiale et temporelle, est une technique bien connue pour réduire l'énergie et augmenter les performances. Cependant, après des transformations améliorant la localité, le calcul des adresses devient souvent un goulot d'étranglement. Dans cet article, nous proposons une nouvelle technique d’exploration et de cartographie AGU (Address Generation Unit) basée sur un modèle AGU reconfigurable. Les résultats expérimentaux montrent que les techniques proposées aident à explorer efficacement les architectures AGU et que les concepteurs peuvent obtenir des compromis sur des applications réelles pendant environ 10 heures.
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Ittetsu TANIGUCHI, Praveen RAGHAVAN, Murali JAYAPALA, Francky CATTHOOR, Yoshinori TAKEUCHI, Masaharu IMAI, "Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 4, pp. 1161-1173, April 2009, doi: 10.1587/transfun.E92.A.1161.
Abstract: Low energy and high performance embedded processor is crucial in the future nomadic embedded systems design. Improvement of memory accesses, especially improvement of spatial and temporal locality is well known technique to reduce energy and increase performance. However, after transformations that improve locality, address calculation often becomes a bottleneck. In this paper, we propose novel AGU (Address Generation Unit) exploration and mapping technique based on a reconfigurable AGU model. Experimental results show that the proposed techniques help exploring AGU architectures effectively and designers can get trade-offs of real life applications for about 10 hours.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.1161/_p
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@ARTICLE{e92-a_4_1161,
author={Ittetsu TANIGUCHI, Praveen RAGHAVAN, Murali JAYAPALA, Francky CATTHOOR, Yoshinori TAKEUCHI, Masaharu IMAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors},
year={2009},
volume={E92-A},
number={4},
pages={1161-1173},
abstract={Low energy and high performance embedded processor is crucial in the future nomadic embedded systems design. Improvement of memory accesses, especially improvement of spatial and temporal locality is well known technique to reduce energy and increase performance. However, after transformations that improve locality, address calculation often becomes a bottleneck. In this paper, we propose novel AGU (Address Generation Unit) exploration and mapping technique based on a reconfigurable AGU model. Experimental results show that the proposed techniques help exploring AGU architectures effectively and designers can get trade-offs of real life applications for about 10 hours.},
keywords={},
doi={10.1587/transfun.E92.A.1161},
ISSN={1745-1337},
month={April},}
Copier
TY - JOUR
TI - Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1161
EP - 1173
AU - Ittetsu TANIGUCHI
AU - Praveen RAGHAVAN
AU - Murali JAYAPALA
AU - Francky CATTHOOR
AU - Yoshinori TAKEUCHI
AU - Masaharu IMAI
PY - 2009
DO - 10.1587/transfun.E92.A.1161
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2009
AB - Low energy and high performance embedded processor is crucial in the future nomadic embedded systems design. Improvement of memory accesses, especially improvement of spatial and temporal locality is well known technique to reduce energy and increase performance. However, after transformations that improve locality, address calculation often becomes a bottleneck. In this paper, we propose novel AGU (Address Generation Unit) exploration and mapping technique based on a reconfigurable AGU model. Experimental results show that the proposed techniques help exploring AGU architectures effectively and designers can get trade-offs of real life applications for about 10 hours.
ER -