The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Pour les VLSI récents et futurs de technologie nanométrique, les variations de retard statiques et dynamiques deviennent un problème sérieux. Dans de nombreux cas, la contrainte de maintien, ainsi que la contrainte de configuration, deviennent critiques pour verrouiller un signal correct sous des variations de retard. Cet article traite de la contrainte de maintien dans un circuit de chemin de données et discute d'une affectation de registre en synthèse de haut niveau en considérant les variations de retard. Notre approche pour garantir la contrainte de maintien sous les variations de délai consiste à élargir le délai de trajet minimum entre les registres, appelé compensation de délai de trajet minimum (MDC) dans cet article. Le MDC peut être réalisé en insérant des éléments de retard principalement dans les chemins non critiques d'une unité fonctionnelle (FU). Une de nos contributions est de montrer que la minimisation du nombre de FU compensées avec un retard de trajet minimum est NP-difficile en général, et qu'elle est dans la classe P si le nombre de FU est constant. Un algorithme en temps polynomial pour ces derniers est également présenté dans cet article. De plus, une formulation de programmation linéaire en nombre entier (ILP) est également présentée. Le procédé proposé génère un chemin de données ayant (1) une robustesse contre les variations de retard, qui est assurée en partie par la technique MDC et en partie par une attribution de registre basée sur SRV, et (2) le nombre minimum possible de MDC et de registres.
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Keisuke INOUE, Mineo KANEKO, Tsuyoshi IWAGAKI, "Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 4, pp. 1096-1105, April 2009, doi: 10.1587/transfun.E92.A.1096.
Abstract: For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold constraint, as well as the setup constraint, becomes critical for latching a correct signal under delay variations. This paper treats the hold constraint in a datapath circuit, and discusses a register assignment in high level synthesis considering delay variations. Our approach to ensure the hold constraint under delay variations is to enlarge the minimum-path delay between registers, which is called minimum-path delay compensation (MDC) in this paper. MDC can be done by inserting delay elements mainly in non-critical paths of a functional unit (FU). One of our contributions is to show that the minimization of the number of minimum-path delay compensated FUs is NP-hard in general, and it is in the class P if the number of FUs is a constant. A polynomial time algorithm for the latter is also shown in this paper. In addition, an integer linear programming (ILP) formulation is also presented. The proposed method generates a datapath having (1) robustness against delay variations, which is ensured partly by MDC technique and partly by SRV-based register assignment, and (2) the minimum possible numbers of MDCs and registers.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.1096/_p
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@ARTICLE{e92-a_4_1096,
author={Keisuke INOUE, Mineo KANEKO, Tsuyoshi IWAGAKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths},
year={2009},
volume={E92-A},
number={4},
pages={1096-1105},
abstract={For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold constraint, as well as the setup constraint, becomes critical for latching a correct signal under delay variations. This paper treats the hold constraint in a datapath circuit, and discusses a register assignment in high level synthesis considering delay variations. Our approach to ensure the hold constraint under delay variations is to enlarge the minimum-path delay between registers, which is called minimum-path delay compensation (MDC) in this paper. MDC can be done by inserting delay elements mainly in non-critical paths of a functional unit (FU). One of our contributions is to show that the minimization of the number of minimum-path delay compensated FUs is NP-hard in general, and it is in the class P if the number of FUs is a constant. A polynomial time algorithm for the latter is also shown in this paper. In addition, an integer linear programming (ILP) formulation is also presented. The proposed method generates a datapath having (1) robustness against delay variations, which is ensured partly by MDC technique and partly by SRV-based register assignment, and (2) the minimum possible numbers of MDCs and registers.},
keywords={},
doi={10.1587/transfun.E92.A.1096},
ISSN={1745-1337},
month={April},}
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TY - JOUR
TI - Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1096
EP - 1105
AU - Keisuke INOUE
AU - Mineo KANEKO
AU - Tsuyoshi IWAGAKI
PY - 2009
DO - 10.1587/transfun.E92.A.1096
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2009
AB - For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold constraint, as well as the setup constraint, becomes critical for latching a correct signal under delay variations. This paper treats the hold constraint in a datapath circuit, and discusses a register assignment in high level synthesis considering delay variations. Our approach to ensure the hold constraint under delay variations is to enlarge the minimum-path delay between registers, which is called minimum-path delay compensation (MDC) in this paper. MDC can be done by inserting delay elements mainly in non-critical paths of a functional unit (FU). One of our contributions is to show that the minimization of the number of minimum-path delay compensated FUs is NP-hard in general, and it is in the class P if the number of FUs is a constant. A polynomial time algorithm for the latter is also shown in this paper. In addition, an integer linear programming (ILP) formulation is also presented. The proposed method generates a datapath having (1) robustness against delay variations, which is ensured partly by MDC technique and partly by SRV-based register assignment, and (2) the minimum possible numbers of MDCs and registers.
ER -