The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Une puce tampon de transmission de 3 Gbit/s/voie comprenant un détecteur de mode haute vitesse est proposée pour un générateur de trames basé sur un réseau de portes programmable sur site (FPGA) prenant en charge l'interface de processeur industriel mobile (MIPI) D-PHY version 1.2. Il effectue une répétition de 1 à 3 tout en mettant en mémoire tampon la signalisation différentielle basse tension (LVDS) ou la signalisation basse tension évolutive (SLVS) vers SLVS.
Pil-Ho LEE
Kumoh National Institute of Technology
Young-Chan JANG
Kumoh National Institute of Technology
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Copier
Pil-Ho LEE, Young-Chan JANG, "A 3Gbps/Lane MIPI D-PHY Transmission Buffer Chip" in IEICE TRANSACTIONS on Fundamentals,
vol. E102-A, no. 6, pp. 783-787, June 2019, doi: 10.1587/transfun.E102.A.783.
Abstract: A 3Gbps/lane transmission buffer chip including a high-speed mode detector is proposed for a field-programmable gate array (FPGA)-based frame generator supporting the mobile industry processor interface (MIPI) D-PHY version 1.2. It performs 1-to-3 repeat while buffering low voltage differential signaling (LVDS) or scalable low voltage signaling (SLVS) to SLVS.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E102.A.783/_p
Copier
@ARTICLE{e102-a_6_783,
author={Pil-Ho LEE, Young-Chan JANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 3Gbps/Lane MIPI D-PHY Transmission Buffer Chip},
year={2019},
volume={E102-A},
number={6},
pages={783-787},
abstract={A 3Gbps/lane transmission buffer chip including a high-speed mode detector is proposed for a field-programmable gate array (FPGA)-based frame generator supporting the mobile industry processor interface (MIPI) D-PHY version 1.2. It performs 1-to-3 repeat while buffering low voltage differential signaling (LVDS) or scalable low voltage signaling (SLVS) to SLVS.},
keywords={},
doi={10.1587/transfun.E102.A.783},
ISSN={1745-1337},
month={June},}
Copier
TY - JOUR
TI - A 3Gbps/Lane MIPI D-PHY Transmission Buffer Chip
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 783
EP - 787
AU - Pil-Ho LEE
AU - Young-Chan JANG
PY - 2019
DO - 10.1587/transfun.E102.A.783
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E102-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2019
AB - A 3Gbps/lane transmission buffer chip including a high-speed mode detector is proposed for a field-programmable gate array (FPGA)-based frame generator supporting the mobile industry processor interface (MIPI) D-PHY version 1.2. It performs 1-to-3 repeat while buffering low voltage differential signaling (LVDS) or scalable low voltage signaling (SLVS) to SLVS.
ER -