The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Nous avons proposé une architecture générique capable d'intégrer les aspects de confidentialité et d'intégrité dans le cadre de conversion A/D. Un compte rendu conceptuel du développement de l'architecture proposée est présenté. En utilisant le principe de cette architecture, nous avons présenté une conception de circuit CMOS pour faciliter un ADC authentifié-crypté (AE-ADC) entièrement intégré. Nous avons implémenté et démontré un frontal analogique ADC 8 bits partiel de ce circuit proposé en CMOS 0.18 µm avec un ENOB de 7.64 bits.
Vinod V. GADDE
The University of Tokyo
Makoto IKEDA
The University of Tokyo
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Vinod V. GADDE, Makoto IKEDA, "Authenticated-Encrypted Analog-to-Digital Conversion Based on Non-Linearity and Redundancy Transformation" in IEICE TRANSACTIONS on Fundamentals,
vol. E102-A, no. 12, pp. 1731-1740, December 2019, doi: 10.1587/transfun.E102.A.1731.
Abstract: We have proposed a generic architecture that can integrate the aspects of confidentiality and integrity into the A/D conversion framework. A conceptual account of the development of the proposed architecture is presented. Using the principle of this architecture we have presented a CMOS circuit design to facilitate a fully integrated Authenticated-Encrypted ADC (AE-ADC). We have implemented and demonstrated a partial 8-bit ADC Analog Front End of this proposed circuit in 0.18µm CMOS with an ENOB of 7.64 bits.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E102.A.1731/_p
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@ARTICLE{e102-a_12_1731,
author={Vinod V. GADDE, Makoto IKEDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Authenticated-Encrypted Analog-to-Digital Conversion Based on Non-Linearity and Redundancy Transformation},
year={2019},
volume={E102-A},
number={12},
pages={1731-1740},
abstract={We have proposed a generic architecture that can integrate the aspects of confidentiality and integrity into the A/D conversion framework. A conceptual account of the development of the proposed architecture is presented. Using the principle of this architecture we have presented a CMOS circuit design to facilitate a fully integrated Authenticated-Encrypted ADC (AE-ADC). We have implemented and demonstrated a partial 8-bit ADC Analog Front End of this proposed circuit in 0.18µm CMOS with an ENOB of 7.64 bits.},
keywords={},
doi={10.1587/transfun.E102.A.1731},
ISSN={1745-1337},
month={December},}
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TY - JOUR
TI - Authenticated-Encrypted Analog-to-Digital Conversion Based on Non-Linearity and Redundancy Transformation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1731
EP - 1740
AU - Vinod V. GADDE
AU - Makoto IKEDA
PY - 2019
DO - 10.1587/transfun.E102.A.1731
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E102-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2019
AB - We have proposed a generic architecture that can integrate the aspects of confidentiality and integrity into the A/D conversion framework. A conceptual account of the development of the proposed architecture is presented. Using the principle of this architecture we have presented a CMOS circuit design to facilitate a fully integrated Authenticated-Encrypted ADC (AE-ADC). We have implemented and demonstrated a partial 8-bit ADC Analog Front End of this proposed circuit in 0.18µm CMOS with an ENOB of 7.64 bits.
ER -