The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article présente une implémentation FPGA de la synthèse HDR (High Dynamic Range) en temps réel, qui exprime une large plage dynamique en combinant plusieurs images avec différentes expositions à l'aide de pyramides d'images. Nous avons implémenté un pipeline qui effectue un traitement en streaming sur les images sans utiliser de mémoire externe. Cependant, la mise en œuvre d'images haute résolution a été difficile en raison de l'utilisation importante de la mémoire pour les tampons de ligne. Par conséquent, nous proposons un algorithme de compression d’image basé sur la modulation adaptative différentielle par impulsions et code (ADPCM). Les modules de compression basés sur l'algorithme peuvent être facilement intégrés dans le pipeline. Lorsque la résolution de l'image est de 4K et la profondeur de la pyramide de 7, l'utilisation de la mémoire peut être réduite de moitié, passant de 168.48 % à 84.32 % en introduisant les modules de compression, ce qui permet d'obtenir une meilleure qualité.
Masahiro NISHIMURA
Nagasaki University
Taito MANABE
Nagasaki University
Yuichiro SHIBATA
Nagasaki University
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Masahiro NISHIMURA, Taito MANABE, Yuichiro SHIBATA, "Pipelined ADPCM Compression for HDR Synthesis on an FPGA" in IEICE TRANSACTIONS on Fundamentals,
vol. E107-A, no. 3, pp. 531-539, March 2024, doi: 10.1587/transfun.2023VLP0017.
Abstract: This paper presents an FPGA implementation of real-time high dynamic range (HDR) synthesis, which expresses a wide dynamic range by combining multiple images with different exposures using image pyramids. We have implemented a pipeline that performs streaming processing on images without using external memory. However, implementation for high-resolution images has been difficult due to large memory usage for line buffers. Therefore, we propose an image compression algorithm based on adaptive differential pulse code modulation (ADPCM). Compression modules based on the algorithm can be easily integrated into the pipeline. When the image resolution is 4K and the pyramid depth is 7, memory usage can be halved from 168.48% to 84.32% by introducing the compression modules, resulting in better quality.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2023VLP0017/_p
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@ARTICLE{e107-a_3_531,
author={Masahiro NISHIMURA, Taito MANABE, Yuichiro SHIBATA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Pipelined ADPCM Compression for HDR Synthesis on an FPGA},
year={2024},
volume={E107-A},
number={3},
pages={531-539},
abstract={This paper presents an FPGA implementation of real-time high dynamic range (HDR) synthesis, which expresses a wide dynamic range by combining multiple images with different exposures using image pyramids. We have implemented a pipeline that performs streaming processing on images without using external memory. However, implementation for high-resolution images has been difficult due to large memory usage for line buffers. Therefore, we propose an image compression algorithm based on adaptive differential pulse code modulation (ADPCM). Compression modules based on the algorithm can be easily integrated into the pipeline. When the image resolution is 4K and the pyramid depth is 7, memory usage can be halved from 168.48% to 84.32% by introducing the compression modules, resulting in better quality.},
keywords={},
doi={10.1587/transfun.2023VLP0017},
ISSN={1745-1337},
month={March},}
Copier
TY - JOUR
TI - Pipelined ADPCM Compression for HDR Synthesis on an FPGA
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 531
EP - 539
AU - Masahiro NISHIMURA
AU - Taito MANABE
AU - Yuichiro SHIBATA
PY - 2024
DO - 10.1587/transfun.2023VLP0017
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E107-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2024
AB - This paper presents an FPGA implementation of real-time high dynamic range (HDR) synthesis, which expresses a wide dynamic range by combining multiple images with different exposures using image pyramids. We have implemented a pipeline that performs streaming processing on images without using external memory. However, implementation for high-resolution images has been difficult due to large memory usage for line buffers. Therefore, we propose an image compression algorithm based on adaptive differential pulse code modulation (ADPCM). Compression modules based on the algorithm can be easily integrated into the pipeline. When the image resolution is 4K and the pyramid depth is 7, memory usage can be halved from 168.48% to 84.32% by introducing the compression modules, resulting in better quality.
ER -