The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Des appareils de périphérie aux serveurs cloud, fournir une accélération matérielle optimisée pour des applications spécifiques est devenue une approche clé pour améliorer l'efficacité des systèmes informatiques. Traditionnellement, de nombreux systèmes utilisent des réseaux de portes programmables sur site (FPGA) commerciaux pour implémenter un accélérateur matériel dédié en tant que coprocesseur du processeur. Cependant, les FPGA commerciaux sont conçus dans des architectures génériques et sont fournis sous forme de puces discrètes, ce qui rend difficile la satisfaction des besoins de plus en plus diversifiés du marché, comme l'équilibrage de ressources matérielles reconfigurables pour une application spécifique, ou leur intégration dans le système d'un client. sur puce (SoC) sous forme de FPGA embarqué (eFPGA). Dans cet article, nous proposons une suite de génération eFPGA avec une architecture personnalisable et un environnement de développement intégré (IDE), qui couvre l'ensemble des étapes de génération, de test et d'utilisation de la conception eFPGA. Pour la génération de conceptions eFPGA, notre flux de génération de propriété intellectuelle (IP) peut explorer les structures optimales de cellules logiques, de routage et de matrice pour des applications cibles données. Pour la testabilité, nous utilisons une méthode de test d'expédition proposée précédemment qui est précise à 100 % pour détecter tous les défauts bloqués dans l'ensemble du FPGA-IP. De plus, nous proposons un framework IDE basé sur le Web convivial et personnalisable pour l'eFPGA généré, basé sur le framework de développement NODE-RED. Dans l'étude de cas, nous montrons un exemple d'exploration d'architecture eFPGA pour une application de chiffrement différentiel de confidentialité utilisant la suite proposée. Nous montrons ensuite la mise en œuvre et l'évaluation du prototype eFPGA avec une conception de puce de groupe d'éléments de test de 55 nm.
Morihiro KUGA
Kumamoto University
Qian ZHAO
Kyushu Institute of Technology
Yuya NAKAZATO
Kumamoto University
Motoki AMAGASAKI
Kumamoto University
Masahiro IIDA
Kumamoto University
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Morihiro KUGA, Qian ZHAO, Yuya NAKAZATO, Motoki AMAGASAKI, Masahiro IIDA, "An eFPGA Generation Suite with Customizable Architecture and IDE" in IEICE TRANSACTIONS on Fundamentals,
vol. E106-A, no. 3, pp. 560-574, March 2023, doi: 10.1587/transfun.2022VLP0008.
Abstract: From edge devices to cloud servers, providing optimized hardware acceleration for specific applications has become a key approach to improve the efficiency of computer systems. Traditionally, many systems employ commercial field-programmable gate arrays (FPGAs) to implement dedicated hardware accelerator as the CPU's co-processor. However, commercial FPGAs are designed in generic architectures and are provided in the form of discrete chips, which makes it difficult to meet increasingly diversified market needs, such as balancing reconfigurable hardware resources for a specific application, or to be integrated into a customer's system-on-a-chip (SoC) in the form of embedded FPGA (eFPGA). In this paper, we propose an eFPGA generation suite with customizable architecture and integrated development environment (IDE), which covers the entire eFPGA design generation, testing, and utilization stages. For the eFPGA design generation, our intellectual property (IP) generation flow can explore the optimal logic cell, routing, and array structures for given target applications. For the testability, we employ a previously proposed shipping test method that is 100% accurate at detecting all stuck-at faults in the entire FPGA-IP. In addition, we propose a user-friendly and customizable Web-based IDE framework for the generated eFPGA based on the NODE-RED development framework. In the case study, we show an eFPGA architecture exploration example for a differential privacy encryption application using the proposed suite. Then we show the implementation and evaluation of the eFPGA prototype with a 55nm test element group chip design.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2022VLP0008/_p
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@ARTICLE{e106-a_3_560,
author={Morihiro KUGA, Qian ZHAO, Yuya NAKAZATO, Motoki AMAGASAKI, Masahiro IIDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An eFPGA Generation Suite with Customizable Architecture and IDE},
year={2023},
volume={E106-A},
number={3},
pages={560-574},
abstract={From edge devices to cloud servers, providing optimized hardware acceleration for specific applications has become a key approach to improve the efficiency of computer systems. Traditionally, many systems employ commercial field-programmable gate arrays (FPGAs) to implement dedicated hardware accelerator as the CPU's co-processor. However, commercial FPGAs are designed in generic architectures and are provided in the form of discrete chips, which makes it difficult to meet increasingly diversified market needs, such as balancing reconfigurable hardware resources for a specific application, or to be integrated into a customer's system-on-a-chip (SoC) in the form of embedded FPGA (eFPGA). In this paper, we propose an eFPGA generation suite with customizable architecture and integrated development environment (IDE), which covers the entire eFPGA design generation, testing, and utilization stages. For the eFPGA design generation, our intellectual property (IP) generation flow can explore the optimal logic cell, routing, and array structures for given target applications. For the testability, we employ a previously proposed shipping test method that is 100% accurate at detecting all stuck-at faults in the entire FPGA-IP. In addition, we propose a user-friendly and customizable Web-based IDE framework for the generated eFPGA based on the NODE-RED development framework. In the case study, we show an eFPGA architecture exploration example for a differential privacy encryption application using the proposed suite. Then we show the implementation and evaluation of the eFPGA prototype with a 55nm test element group chip design.},
keywords={},
doi={10.1587/transfun.2022VLP0008},
ISSN={1745-1337},
month={March},}
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TY - JOUR
TI - An eFPGA Generation Suite with Customizable Architecture and IDE
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 560
EP - 574
AU - Morihiro KUGA
AU - Qian ZHAO
AU - Yuya NAKAZATO
AU - Motoki AMAGASAKI
AU - Masahiro IIDA
PY - 2023
DO - 10.1587/transfun.2022VLP0008
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E106-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2023
AB - From edge devices to cloud servers, providing optimized hardware acceleration for specific applications has become a key approach to improve the efficiency of computer systems. Traditionally, many systems employ commercial field-programmable gate arrays (FPGAs) to implement dedicated hardware accelerator as the CPU's co-processor. However, commercial FPGAs are designed in generic architectures and are provided in the form of discrete chips, which makes it difficult to meet increasingly diversified market needs, such as balancing reconfigurable hardware resources for a specific application, or to be integrated into a customer's system-on-a-chip (SoC) in the form of embedded FPGA (eFPGA). In this paper, we propose an eFPGA generation suite with customizable architecture and integrated development environment (IDE), which covers the entire eFPGA design generation, testing, and utilization stages. For the eFPGA design generation, our intellectual property (IP) generation flow can explore the optimal logic cell, routing, and array structures for given target applications. For the testability, we employ a previously proposed shipping test method that is 100% accurate at detecting all stuck-at faults in the entire FPGA-IP. In addition, we propose a user-friendly and customizable Web-based IDE framework for the generated eFPGA based on the NODE-RED development framework. In the case study, we show an eFPGA architecture exploration example for a differential privacy encryption application using the proposed suite. Then we show the implementation and evaluation of the eFPGA prototype with a 55nm test element group chip design.
ER -