The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Un bus partagé de 6.5 Gb/s qui utilise une puce émettrice-réceptrice d'impulsions CMOS 65 nm avec un égaliseur basse fréquence et des connecteurs électromagnétiques basés sur deux types de coupleurs de ligne de transmission est présenté. La quantité de câblage du fond de panier est réduite d'un facteur de 1/16 et le volume total des connecteurs d'un facteur de 1/246. Il réduit la taille et le poids d'un système de processeur satellite de 60 %, augmente le débit de données d'un facteur 2.6 et satisfait à la norme EMC pour résister aux forts chocs du lancement d'une fusée.
Atsutake KOSUGE
The Univ. of Tokyo
Mototsugu HAMADA
The Univ. of Tokyo
Tadahiro KURODA
The Univ. of Tokyo
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Atsutake KOSUGE, Mototsugu HAMADA, Tadahiro KURODA, "A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System" in IEICE TRANSACTIONS on Fundamentals,
vol. E105-A, no. 3, pp. 478-486, March 2022, doi: 10.1587/transfun.2021VLP0001.
Abstract: A 6.5Gb/s shared bus that uses a 65nm CMOS pulse transceiver chip with a low frequency equalizer and electromagnetic connectors based on two types of transmission line couplers is presented. The amount of backplane wiring is reduced by a factor of 1/16 and total connector volume by a factor of 1/246. It reduces the size and weight of a satellite processor system by 60%, increases the data rate by a factor of 2.6, and satisfies the EMC standard for withstanding the strong shock of rocket launch.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2021VLP0001/_p
Copier
@ARTICLE{e105-a_3_478,
author={Atsutake KOSUGE, Mototsugu HAMADA, Tadahiro KURODA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System},
year={2022},
volume={E105-A},
number={3},
pages={478-486},
abstract={A 6.5Gb/s shared bus that uses a 65nm CMOS pulse transceiver chip with a low frequency equalizer and electromagnetic connectors based on two types of transmission line couplers is presented. The amount of backplane wiring is reduced by a factor of 1/16 and total connector volume by a factor of 1/246. It reduces the size and weight of a satellite processor system by 60%, increases the data rate by a factor of 2.6, and satisfies the EMC standard for withstanding the strong shock of rocket launch.},
keywords={},
doi={10.1587/transfun.2021VLP0001},
ISSN={1745-1337},
month={March},}
Copier
TY - JOUR
TI - A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 478
EP - 486
AU - Atsutake KOSUGE
AU - Mototsugu HAMADA
AU - Tadahiro KURODA
PY - 2022
DO - 10.1587/transfun.2021VLP0001
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E105-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2022
AB - A 6.5Gb/s shared bus that uses a 65nm CMOS pulse transceiver chip with a low frequency equalizer and electromagnetic connectors based on two types of transmission line couplers is presented. The amount of backplane wiring is reduced by a factor of 1/16 and total connector volume by a factor of 1/246. It reduces the size and weight of a satellite processor system by 60%, increases the data rate by a factor of 2.6, and satisfies the EMC standard for withstanding the strong shock of rocket launch.
ER -