The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
La menace croissante des chevaux de Troie matériels (HT) dans l'industrie des systèmes sur puces (SoC) a incité les chercheurs en systèmes embarqués à proposer une série de méthodologies de détection pour identifier et détecter la présence de circuits ou de logiques de chevaux de Troie à l'intérieur d'une conception hôte. dans les différentes étapes du processus de conception et de fabrication des puces. De nombreux travaux de pointe proposent différentes techniques de détection HT parmi lesquelles le choix populaire reste les méthodes basées sur l'analyse par canal latéral (SCA) qui effectuent une analyse différentielle ciblant la différence de consommation d'énergie, la modification de l'émanation électromagnétique ou le retard de propagation de l'énergie électromagnétique. logique dans les différents chemins du circuit. Même si l'efficacité de ces méthodes est bien établie, l'évaluation est réalisée sur des modèles simplistes tels que les coprocesseurs AES et les approches analytiques utilisées pour ces méthodes sont limitées par certaines métriques statistiques telles que la comparaison directe des traces EM ou les coefficients du test T. . Dans cet article, nous proposons deux nouvelles méthodologies de détection basées sur des algorithmes de Machine Learning. La première méthode consiste à appliquer les algorithmes de Machine Learning (ML) supervisé sur des traces EM brutes pour la classification et la détection des HT. Il offre un taux de détection proche de 90 % et des faux négatifs inférieurs à 5 %. Dans la deuxième méthode, nous proposons une approche basée sur des algorithmes aberrants/nouveautés. Cette méthode combinée à la technique de traitement du signal basée sur le test T, par rapport à l'état de l'art, offre de meilleures performances avec un taux de détection proche de 100 % et un faux positif inférieur à 1 %. Dans différentes expériences, le faux négatif est presque au même niveau que le faux positif et pour cette raison les auteurs montrent uniquement la valeur du faux positif sur les résultats. Nous avons évalué les performances de notre méthode sur une conception cible complexe : le processeur générique RISC-V. Trois HT avec leurs tailles correspondantes : 0.53 %, 0.27 % et 0.09 % des processeurs RISC-V sont insérés pour l'expérimentation. Dans cet article, nous fournissons des détails élaborés sur nos tests et notre processus expérimental pour la reproductibilité. Les résultats expérimentaux montrent que les HT insérés, bien que minimalistes, peuvent être détectés avec succès grâce à notre nouvelle méthodologie.
Junko TAKAHASHI
NTT Social Informatics Laboratories
Keiichi OKABE
NTT Secure Platform Laboratories
Hiroki ITOH
NTT Social Informatics Laboratories
Xuan-Thuy NGO
Cesson-Sevigne
Sylvain GUILLEY
Cesson-Sevigne
Ritu-Ranjan SHRIVASTWA
Cesson-Sevigne
Mushir AHMED
Cesson-Sevigne
Patrick LEJOLY
Cesson-Sevigne
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Junko TAKAHASHI, Keiichi OKABE, Hiroki ITOH, Xuan-Thuy NGO, Sylvain GUILLEY, Ritu-Ranjan SHRIVASTWA, Mushir AHMED, Patrick LEJOLY, "Machine Learning Based Hardware Trojan Detection Using Electromagnetic Emanation" in IEICE TRANSACTIONS on Fundamentals,
vol. E105-A, no. 3, pp. 311-325, March 2022, doi: 10.1587/transfun.2021CIP0011.
Abstract: The growing threat of Hardware Trojans (HT) in the System-on-Chips (SoC) industry has given way to the embedded systems researchers to propose a series of detection methodologies to identify and detect the presence of Trojan circuits or logics inside a host design in the various stages of the chip design and manufacturing process. Many state of the art works propose different techniques for HT detection among which the popular choice remains the Side-Channel Analysis (SCA) based methods that perform differential analysis targeting the difference in consumption of power, change in electromagnetic emanation or the delay in propagation of logic in various paths of the circuit. Even though the effectiveness of these methods are well established, the evaluation is carried out on simplistic models such as AES coprocessors and the analytical approaches used for these methods are limited by some statistical metrics such as direct comparison of EM traces or the T-test coefficients. In this paper, we propose two new detection methodologies based on Machine Learning algorithms. The first method consists in applying the supervised Machine Learning (ML) algorithms on raw EM traces for the classification and detection of HT. It offers a detection rate close to 90% and false negative smaller than 5%. In the second method, we propose an outlier/novelty algorithms based approach. This method combined with the T-test based signal processing technique, when compared with state-of-the-art, offers a better performance with a detection rate close to 100% and a false positive smaller than 1%. In different experiments, the false negative is nearly the same level than the false positive and for that reason the authors only show the false positive value on the results. We have evaluated the performance of our method on a complex target design: RISC-V generic processor. Three HTs with their corresponding sizes: 0.53%, 0.27% and 0.09% of the RISC-V processors are inserted for the experimentation. In this paper we provide elaborative details of our tests and experimental process for reproducibility. The experimental results show that the inserted HTs, though minimalistic, can be successfully detected using our new methodology.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2021CIP0011/_p
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@ARTICLE{e105-a_3_311,
author={Junko TAKAHASHI, Keiichi OKABE, Hiroki ITOH, Xuan-Thuy NGO, Sylvain GUILLEY, Ritu-Ranjan SHRIVASTWA, Mushir AHMED, Patrick LEJOLY, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Machine Learning Based Hardware Trojan Detection Using Electromagnetic Emanation},
year={2022},
volume={E105-A},
number={3},
pages={311-325},
abstract={The growing threat of Hardware Trojans (HT) in the System-on-Chips (SoC) industry has given way to the embedded systems researchers to propose a series of detection methodologies to identify and detect the presence of Trojan circuits or logics inside a host design in the various stages of the chip design and manufacturing process. Many state of the art works propose different techniques for HT detection among which the popular choice remains the Side-Channel Analysis (SCA) based methods that perform differential analysis targeting the difference in consumption of power, change in electromagnetic emanation or the delay in propagation of logic in various paths of the circuit. Even though the effectiveness of these methods are well established, the evaluation is carried out on simplistic models such as AES coprocessors and the analytical approaches used for these methods are limited by some statistical metrics such as direct comparison of EM traces or the T-test coefficients. In this paper, we propose two new detection methodologies based on Machine Learning algorithms. The first method consists in applying the supervised Machine Learning (ML) algorithms on raw EM traces for the classification and detection of HT. It offers a detection rate close to 90% and false negative smaller than 5%. In the second method, we propose an outlier/novelty algorithms based approach. This method combined with the T-test based signal processing technique, when compared with state-of-the-art, offers a better performance with a detection rate close to 100% and a false positive smaller than 1%. In different experiments, the false negative is nearly the same level than the false positive and for that reason the authors only show the false positive value on the results. We have evaluated the performance of our method on a complex target design: RISC-V generic processor. Three HTs with their corresponding sizes: 0.53%, 0.27% and 0.09% of the RISC-V processors are inserted for the experimentation. In this paper we provide elaborative details of our tests and experimental process for reproducibility. The experimental results show that the inserted HTs, though minimalistic, can be successfully detected using our new methodology.},
keywords={},
doi={10.1587/transfun.2021CIP0011},
ISSN={1745-1337},
month={March},}
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TY - JOUR
TI - Machine Learning Based Hardware Trojan Detection Using Electromagnetic Emanation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 311
EP - 325
AU - Junko TAKAHASHI
AU - Keiichi OKABE
AU - Hiroki ITOH
AU - Xuan-Thuy NGO
AU - Sylvain GUILLEY
AU - Ritu-Ranjan SHRIVASTWA
AU - Mushir AHMED
AU - Patrick LEJOLY
PY - 2022
DO - 10.1587/transfun.2021CIP0011
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E105-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2022
AB - The growing threat of Hardware Trojans (HT) in the System-on-Chips (SoC) industry has given way to the embedded systems researchers to propose a series of detection methodologies to identify and detect the presence of Trojan circuits or logics inside a host design in the various stages of the chip design and manufacturing process. Many state of the art works propose different techniques for HT detection among which the popular choice remains the Side-Channel Analysis (SCA) based methods that perform differential analysis targeting the difference in consumption of power, change in electromagnetic emanation or the delay in propagation of logic in various paths of the circuit. Even though the effectiveness of these methods are well established, the evaluation is carried out on simplistic models such as AES coprocessors and the analytical approaches used for these methods are limited by some statistical metrics such as direct comparison of EM traces or the T-test coefficients. In this paper, we propose two new detection methodologies based on Machine Learning algorithms. The first method consists in applying the supervised Machine Learning (ML) algorithms on raw EM traces for the classification and detection of HT. It offers a detection rate close to 90% and false negative smaller than 5%. In the second method, we propose an outlier/novelty algorithms based approach. This method combined with the T-test based signal processing technique, when compared with state-of-the-art, offers a better performance with a detection rate close to 100% and a false positive smaller than 1%. In different experiments, the false negative is nearly the same level than the false positive and for that reason the authors only show the false positive value on the results. We have evaluated the performance of our method on a complex target design: RISC-V generic processor. Three HTs with their corresponding sizes: 0.53%, 0.27% and 0.09% of the RISC-V processors are inserted for the experimentation. In this paper we provide elaborative details of our tests and experimental process for reproducibility. The experimental results show that the inserted HTs, though minimalistic, can be successfully detected using our new methodology.
ER -