The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article présente un circuit intégré d'amplificateur de puissance (PA) à haut rendement de réduction de la bande de 26 GHz avec des circuits de polarisation et de charge à commande adaptative dans un SOI CMOS de 45 nm. Un FET à 4 piles est utilisé pour augmenter la puissance de sortie et résoudre le problème de faible tension de claquage des MOSFET à l'échelle. Le circuit de polarisation adaptative est examiné et le circuit de charge adaptative qui se compose d'un circuit onduleur et d'inductances basées sur un transformateur est décrit en détail. Les performances mesurées du PA IC sont entièrement présentées dans cet article. Le PA IC présente une puissance de sortie saturée de 20.5 dBm et un rendement de puissance ajoutée (PAE) maximal pouvant atteindre 39.4 % à une tension d'alimentation de 4.0 V. De plus, le PA IC a présenté un excellent ITRS FoM de 82.0 dB.
Toshihiko YOSHIMASU
Waseda University
Mengchu FANG
Waseda University
Tsuyoshi SUGIURA
the Samsung R&D Institute Japan
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Toshihiko YOSHIMASU, Mengchu FANG, Tsuyoshi SUGIURA, "A 26-GHz-Band High Back-Off Efficiency Stacked-FET Power Amplifier IC with Adaptively Controlled Bias and Load Circuits in 45-nm CMOS SOI" in IEICE TRANSACTIONS on Fundamentals,
vol. E104-A, no. 2, pp. 477-483, February 2021, doi: 10.1587/transfun.2020GCP0012.
Abstract: This paper presents a 26-GHz-band high back-off efficiency power amplifier (PA) IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI. A 4-stacked-FET is employed to increase the output power and to conquer the low breakdown voltage issue of scaled MOSFET. The adaptive bias circuit is reviewed and the adaptive load circuit which consists of an inverter circuit and transformer-based inductors is described in detail. The measured performance of the PA IC is fully shown in this paper. The PA IC exhibits a saturated output power of 20.5dBm and a peak power-added-efficiency (PAE) as high as 39.4% at a supply voltage of 4.0V. Moreover, the PA IC has exhibited an excellent ITRS FoM of 82.0dB.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2020GCP0012/_p
Copier
@ARTICLE{e104-a_2_477,
author={Toshihiko YOSHIMASU, Mengchu FANG, Tsuyoshi SUGIURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 26-GHz-Band High Back-Off Efficiency Stacked-FET Power Amplifier IC with Adaptively Controlled Bias and Load Circuits in 45-nm CMOS SOI},
year={2021},
volume={E104-A},
number={2},
pages={477-483},
abstract={This paper presents a 26-GHz-band high back-off efficiency power amplifier (PA) IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI. A 4-stacked-FET is employed to increase the output power and to conquer the low breakdown voltage issue of scaled MOSFET. The adaptive bias circuit is reviewed and the adaptive load circuit which consists of an inverter circuit and transformer-based inductors is described in detail. The measured performance of the PA IC is fully shown in this paper. The PA IC exhibits a saturated output power of 20.5dBm and a peak power-added-efficiency (PAE) as high as 39.4% at a supply voltage of 4.0V. Moreover, the PA IC has exhibited an excellent ITRS FoM of 82.0dB.},
keywords={},
doi={10.1587/transfun.2020GCP0012},
ISSN={1745-1337},
month={February},}
Copier
TY - JOUR
TI - A 26-GHz-Band High Back-Off Efficiency Stacked-FET Power Amplifier IC with Adaptively Controlled Bias and Load Circuits in 45-nm CMOS SOI
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 477
EP - 483
AU - Toshihiko YOSHIMASU
AU - Mengchu FANG
AU - Tsuyoshi SUGIURA
PY - 2021
DO - 10.1587/transfun.2020GCP0012
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E104-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2021
AB - This paper presents a 26-GHz-band high back-off efficiency power amplifier (PA) IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI. A 4-stacked-FET is employed to increase the output power and to conquer the low breakdown voltage issue of scaled MOSFET. The adaptive bias circuit is reviewed and the adaptive load circuit which consists of an inverter circuit and transformer-based inductors is described in detail. The measured performance of the PA IC is fully shown in this paper. The PA IC exhibits a saturated output power of 20.5dBm and a peak power-added-efficiency (PAE) as high as 39.4% at a supply voltage of 4.0V. Moreover, the PA IC has exhibited an excellent ITRS FoM of 82.0dB.
ER -