The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Pour résoudre les problèmes de surface et de puissance dans les implémentations de réponse impulsionnelle finie (FIR), une conception FIR fidèlement tronquée basée sur un additionneur est présentée dans cet article pour des économies significatives de surface et de puissance tout en permettant d'obtenir la précision de sortie prédéfinie. Comme solution à la perte de précision causée par les additionneurs tronqués, une analyse d'erreur statique sur l'utilisation des additionneurs tronqués dans les FIR a été réalisée. Selon l'analyse mathématique, nous montrons que, avec une contrainte de précision donnée, la configuration optimale de l'additionneur tronqué pour une conception FIR efficace en termes de puissance de zone peut être déterminée sans effort. Les résultats de l'évaluation de diverses implémentations FIR en utilisant les conceptions d'additionneurs fidèlement tronquées proposées ont montré que jusqu'à 35.4 % et 27.9 % d'économies en termes de surface et de consommation d'énergie peuvent être obtenues avec moins de 1 ulp perte de précision pour les entrées aléatoires uniformément distribuées. De plus, comme étude de cas pour les signaux normalement distribués, un FIR fixe à 6 prises est implémenté pour le filtrage des signaux d'électrocardiogramme (ECG), dans lequel même avec l'augmentation des bits tronqués jusqu'à 10, l'erreur absolue moyenne (Ē) peut être garanti inférieur à 1 ulp tandis que jusqu'à 29.7 % et 25.3 % d'économies de surface et d'énergie peuvent être obtenues.
Jinghao YE
Waseda University
Masao YANAGISAWA
Waseda University
Youhua SHI
Waseda University
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copier
Jinghao YE, Masao YANAGISAWA, Youhua SHI, "Faithfully Truncated Adder-Based Area-Power Efficient FIR Design with Predefined Output Accuracy" in IEICE TRANSACTIONS on Fundamentals,
vol. E103-A, no. 9, pp. 1063-1070, September 2020, doi: 10.1587/transfun.2019KEP0010.
Abstract: To solve the area and power problems in Finite Impulse Response (FIR) implementations, a faithfully truncated adder-based FIR design is presented in this paper for significant area and power savings while the predefined output accuracy can still be obtained. As a solution to the accuracy loss caused by truncated adders, a static error analysis on the utilization of truncated adders in FIRs was performed. According to the mathematical analysis, we show that, with a given accuracy constraint, the optimal truncated adder configuration for an area-power efficient FIR design can be effortlessly determined. Evaluation results on various FIR implementations by using the proposed faithfully truncated adder designs showed that up to 35.4% and 27.9% savings in area and power consumption can be achieved with less than 1 ulp accuracy loss for uniformly distributed random inputs. Moreover, as a case study for normally distributed signals, a fixed 6-tap FIR is implemented for electrocardiogram (ECG) signal filtering was implemented, in which even with the increased truncated bits up to 10, the mean absolute error (Ē) can be guaranteed to be less than 1 ulp while up to 29.7% and 25.3% savings in area and power can be obtained.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2019KEP0010/_p
Copier
@ARTICLE{e103-a_9_1063,
author={Jinghao YE, Masao YANAGISAWA, Youhua SHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Faithfully Truncated Adder-Based Area-Power Efficient FIR Design with Predefined Output Accuracy},
year={2020},
volume={E103-A},
number={9},
pages={1063-1070},
abstract={To solve the area and power problems in Finite Impulse Response (FIR) implementations, a faithfully truncated adder-based FIR design is presented in this paper for significant area and power savings while the predefined output accuracy can still be obtained. As a solution to the accuracy loss caused by truncated adders, a static error analysis on the utilization of truncated adders in FIRs was performed. According to the mathematical analysis, we show that, with a given accuracy constraint, the optimal truncated adder configuration for an area-power efficient FIR design can be effortlessly determined. Evaluation results on various FIR implementations by using the proposed faithfully truncated adder designs showed that up to 35.4% and 27.9% savings in area and power consumption can be achieved with less than 1 ulp accuracy loss for uniformly distributed random inputs. Moreover, as a case study for normally distributed signals, a fixed 6-tap FIR is implemented for electrocardiogram (ECG) signal filtering was implemented, in which even with the increased truncated bits up to 10, the mean absolute error (Ē) can be guaranteed to be less than 1 ulp while up to 29.7% and 25.3% savings in area and power can be obtained.},
keywords={},
doi={10.1587/transfun.2019KEP0010},
ISSN={1745-1337},
month={September},}
Copier
TY - JOUR
TI - Faithfully Truncated Adder-Based Area-Power Efficient FIR Design with Predefined Output Accuracy
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1063
EP - 1070
AU - Jinghao YE
AU - Masao YANAGISAWA
AU - Youhua SHI
PY - 2020
DO - 10.1587/transfun.2019KEP0010
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E103-A
IS - 9
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - September 2020
AB - To solve the area and power problems in Finite Impulse Response (FIR) implementations, a faithfully truncated adder-based FIR design is presented in this paper for significant area and power savings while the predefined output accuracy can still be obtained. As a solution to the accuracy loss caused by truncated adders, a static error analysis on the utilization of truncated adders in FIRs was performed. According to the mathematical analysis, we show that, with a given accuracy constraint, the optimal truncated adder configuration for an area-power efficient FIR design can be effortlessly determined. Evaluation results on various FIR implementations by using the proposed faithfully truncated adder designs showed that up to 35.4% and 27.9% savings in area and power consumption can be achieved with less than 1 ulp accuracy loss for uniformly distributed random inputs. Moreover, as a case study for normally distributed signals, a fixed 6-tap FIR is implemented for electrocardiogram (ECG) signal filtering was implemented, in which even with the increased truncated bits up to 10, the mean absolute error (Ē) can be guaranteed to be less than 1 ulp while up to 29.7% and 25.3% savings in area and power can be obtained.
ER -