The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dans cette lettre, une réalisation de faible complexité et de faible puissance de la transformée en cosinus discrète 2D et de son inverse (DCT/IDCT) est présentée. Un circuit VLSI basé sur l'algorithme de Chen avec une approche arithmétique distribuée est décrit. De plus, des techniques de conception à faible consommation, basées sur le déclenchement d'horloge et la réduction de l'activité de commutation basée sur les données, sont utilisées pour diminuer la consommation électrique du circuit. Dans ce but, les statistiques des signaux d'entrée ont été extraites des modèles de vérification H.263/MPEG. Enfin, les performances du circuit sont comparées à celles des solutions logicielles connues et à celles dédiées et entièrement personnalisées.
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Luca FANUCCI, Sergio SAPONARA, "Data Driven Power Saving for DCT/IDCT VLSI Macrocell" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 7, pp. 1760-1765, July 2002, doi: .
Abstract: In this letter a low-complexity and low-power realization of the 2D discrete-cosine-transform and its inverse (DCT/IDCT) is presented. A VLSI circuit based on the Chen algorithm with the distributed arithmetic approach is described. Furthermore low-power design techniques, based on clock gating and data driven switching activity reduction, are used to decrease the circuit power consumption. To this aim, input signal statistics have been extracted from H.263/MPEG verification models. Finally, circuit performance is compared to known software solutions and dedicated full-custom ones.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_7_1760/_p
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@ARTICLE{e85-a_7_1760,
author={Luca FANUCCI, Sergio SAPONARA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Data Driven Power Saving for DCT/IDCT VLSI Macrocell},
year={2002},
volume={E85-A},
number={7},
pages={1760-1765},
abstract={In this letter a low-complexity and low-power realization of the 2D discrete-cosine-transform and its inverse (DCT/IDCT) is presented. A VLSI circuit based on the Chen algorithm with the distributed arithmetic approach is described. Furthermore low-power design techniques, based on clock gating and data driven switching activity reduction, are used to decrease the circuit power consumption. To this aim, input signal statistics have been extracted from H.263/MPEG verification models. Finally, circuit performance is compared to known software solutions and dedicated full-custom ones.},
keywords={},
doi={},
ISSN={},
month={July},}
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TY - JOUR
TI - Data Driven Power Saving for DCT/IDCT VLSI Macrocell
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1760
EP - 1765
AU - Luca FANUCCI
AU - Sergio SAPONARA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2002
AB - In this letter a low-complexity and low-power realization of the 2D discrete-cosine-transform and its inverse (DCT/IDCT) is presented. A VLSI circuit based on the Chen algorithm with the distributed arithmetic approach is described. Furthermore low-power design techniques, based on clock gating and data driven switching activity reduction, are used to decrease the circuit power consumption. To this aim, input signal statistics have been extracted from H.263/MPEG verification models. Finally, circuit performance is compared to known software solutions and dedicated full-custom ones.
ER -