The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Un certain nombre d'études ont récemment été publiées concernant des modèles de neurones chaotiques et des réseaux de neurones asynchrones ayant des modèles de neurones chaotiques. Dans le cas de réseaux neuronaux à grande échelle dotés de modèles de neurones chaotiques, le réseau neuronal doit être construit à l'aide de matériel analogique, plutôt que par simulation informatique via un logiciel, en raison de la vitesse élevée et de l'intégration élevée des circuits analogiques. Dans la présente étude, nous discutons de la structure du circuit d’un modèle de neurone chaotique, construit sur la base du modèle mathématique d’un neurone chaotique asynchrone. Nous montrons que le modèle de neurone chaotique matériel de type impulsion peut être construit sur la base du modèle mathématique d'un neurone chaotique asynchrone. Le modèle proposé est un modèle efficace pour la section du corps cellulaire du modèle de neurone chaotique matériel de type impulsionnel pour les circuits intégrés. De plus, nous montrons la structure de bifurcation de notre modèle composé et discutons des itinéraires de bifurcation et de leurs cartes de retour.
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Jun MATSUOKA, Yoshifumi SEKINE, Katsutoshi SAEKI, Kazuyuki AIHARA, "Analog Hardware Implementation of a Mathematical Model of an Asynchronous Chaotic Neuron" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 2, pp. 389-394, February 2002, doi: .
Abstract: A number of studies have recently been published concerning chaotic neuron models and asynchronous neural networks having chaotic neuron models. In the case of large-scale neural networks having chaotic neuron models, the neural network should be constructed using analog hardware, rather than by computer simulation via software, due to the high speed and high integration of analog circuits. In the present study, we discuss the circuit structure of a chaotic neuron model, which is constructed on the basis of the mathematical model of an asynchronous chaotic neuron. We show that the pulse-type hardware chaotic neuron model can be constructed on the basis of the mathematical model of an asynchronous chaotic neuron. The proposed model is an effective model for the cell body section of the pulse-type hardware chaotic neuron model for ICs. In addition, we show the bifurcation structure of our composed model, and discuss the bifurcation routes and return maps thereof.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_2_389/_p
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@ARTICLE{e85-a_2_389,
author={Jun MATSUOKA, Yoshifumi SEKINE, Katsutoshi SAEKI, Kazuyuki AIHARA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Analog Hardware Implementation of a Mathematical Model of an Asynchronous Chaotic Neuron},
year={2002},
volume={E85-A},
number={2},
pages={389-394},
abstract={A number of studies have recently been published concerning chaotic neuron models and asynchronous neural networks having chaotic neuron models. In the case of large-scale neural networks having chaotic neuron models, the neural network should be constructed using analog hardware, rather than by computer simulation via software, due to the high speed and high integration of analog circuits. In the present study, we discuss the circuit structure of a chaotic neuron model, which is constructed on the basis of the mathematical model of an asynchronous chaotic neuron. We show that the pulse-type hardware chaotic neuron model can be constructed on the basis of the mathematical model of an asynchronous chaotic neuron. The proposed model is an effective model for the cell body section of the pulse-type hardware chaotic neuron model for ICs. In addition, we show the bifurcation structure of our composed model, and discuss the bifurcation routes and return maps thereof.},
keywords={},
doi={},
ISSN={},
month={February},}
Copier
TY - JOUR
TI - Analog Hardware Implementation of a Mathematical Model of an Asynchronous Chaotic Neuron
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 389
EP - 394
AU - Jun MATSUOKA
AU - Yoshifumi SEKINE
AU - Katsutoshi SAEKI
AU - Kazuyuki AIHARA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2002
AB - A number of studies have recently been published concerning chaotic neuron models and asynchronous neural networks having chaotic neuron models. In the case of large-scale neural networks having chaotic neuron models, the neural network should be constructed using analog hardware, rather than by computer simulation via software, due to the high speed and high integration of analog circuits. In the present study, we discuss the circuit structure of a chaotic neuron model, which is constructed on the basis of the mathematical model of an asynchronous chaotic neuron. We show that the pulse-type hardware chaotic neuron model can be constructed on the basis of the mathematical model of an asynchronous chaotic neuron. The proposed model is an effective model for the cell body section of the pulse-type hardware chaotic neuron model for ICs. In addition, we show the bifurcation structure of our composed model, and discuss the bifurcation routes and return maps thereof.
ER -