The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Nous présentons le nouveau chiffrement par bloc de 128 bits appelé Camellia. Camellia prend en charge une taille de bloc de 128 bits et des longueurs de clé de 128, 192 et 256 bits, c'est-à-dire les mêmes spécifications d'interface que l'Advanced Encryption Standard (AES). Camellia a été soigneusement conçu pour résister à toutes les attaques cryptanalytiques connues et même pour disposer d'une marge de sécurité suffisamment importante. Il a également été conçu pour s'adapter aux implémentations logicielles et matérielles et pour couvrir toutes les applications de chiffrement possibles, depuis les cartes à puce bon marché jusqu'aux systèmes de réseau à haut débit. Par rapport aux finalistes AES, Camellia offre une vitesse de cryptage au moins comparable en termes de logiciel et de matériel. Une implémentation optimisée de Camellia en langage assembleur permet de chiffrer sur un Pentium III (1.13 GHz) au débit de 471 Mbits par seconde. De plus, une caractéristique distinctive est sa conception matérielle réduite. Une implémentation matérielle, qui inclut le chiffrement, le déchiffrement et la planification des clés pour les clés de 128 bits, n'occupe que 9.66 K portes à l'aide d'une bibliothèque ASIC CMOS de 0.35 µm. Il s'agit de la plus petite classe parmi tous les chiffrements par blocs de 128 bits existants. Il répond parfaitement aux exigences actuelles du marché des cartes sans fil, par exemple, où une faible consommation d'énergie est essentielle.
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Kazumaro AOKI, Tetsuya ICHIKAWA, Masayuki KANDA, Mitsuru MATSUI, Shiho MORIAI, Junko NAKAJIMA, Toshio TOKITA, "The 128-Bit Block Cipher Camellia" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 1, pp. 11-24, January 2002, doi: .
Abstract: We present the new 128-bit block cipher called Camellia. Camellia supports 128-bit block size and 128-, 192-, and 256-bit key lengths, i.e. the same interface specifications as the Advanced Encryption Standard (AES). Camellia was carefully designed to withstand all known cryptanalytic attacks and even to have a sufficiently large security leeway. It was also designed to suit both software and hardware implementations and to cover all possible encryption applications that range from low-cost smart cards to high-speed network systems. Compared to the AES finalists, Camellia offers at least comparable encryption speed in software and hardware. An optimized implementation of Camellia in assembly language can encrypt on a Pentium III (1.13 GHz) at the rate of 471 Mbits per second. In addition, a distinguishing feature is its small hardware design. A hardware implementation, which includes encryption, decryption, and the key schedule for 128-bit keys, occupies only 9.66 K gates using a 0.35 µm CMOS ASIC library. This is in the smallest class among all existing 128-bit block ciphers. It perfectly meets the current market requirements in wireless cards, for instance, where low power consumption is essential.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_1_11/_p
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@ARTICLE{e85-a_1_11,
author={Kazumaro AOKI, Tetsuya ICHIKAWA, Masayuki KANDA, Mitsuru MATSUI, Shiho MORIAI, Junko NAKAJIMA, Toshio TOKITA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={The 128-Bit Block Cipher Camellia},
year={2002},
volume={E85-A},
number={1},
pages={11-24},
abstract={We present the new 128-bit block cipher called Camellia. Camellia supports 128-bit block size and 128-, 192-, and 256-bit key lengths, i.e. the same interface specifications as the Advanced Encryption Standard (AES). Camellia was carefully designed to withstand all known cryptanalytic attacks and even to have a sufficiently large security leeway. It was also designed to suit both software and hardware implementations and to cover all possible encryption applications that range from low-cost smart cards to high-speed network systems. Compared to the AES finalists, Camellia offers at least comparable encryption speed in software and hardware. An optimized implementation of Camellia in assembly language can encrypt on a Pentium III (1.13 GHz) at the rate of 471 Mbits per second. In addition, a distinguishing feature is its small hardware design. A hardware implementation, which includes encryption, decryption, and the key schedule for 128-bit keys, occupies only 9.66 K gates using a 0.35 µm CMOS ASIC library. This is in the smallest class among all existing 128-bit block ciphers. It perfectly meets the current market requirements in wireless cards, for instance, where low power consumption is essential.},
keywords={},
doi={},
ISSN={},
month={January},}
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TY - JOUR
TI - The 128-Bit Block Cipher Camellia
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 11
EP - 24
AU - Kazumaro AOKI
AU - Tetsuya ICHIKAWA
AU - Masayuki KANDA
AU - Mitsuru MATSUI
AU - Shiho MORIAI
AU - Junko NAKAJIMA
AU - Toshio TOKITA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2002
AB - We present the new 128-bit block cipher called Camellia. Camellia supports 128-bit block size and 128-, 192-, and 256-bit key lengths, i.e. the same interface specifications as the Advanced Encryption Standard (AES). Camellia was carefully designed to withstand all known cryptanalytic attacks and even to have a sufficiently large security leeway. It was also designed to suit both software and hardware implementations and to cover all possible encryption applications that range from low-cost smart cards to high-speed network systems. Compared to the AES finalists, Camellia offers at least comparable encryption speed in software and hardware. An optimized implementation of Camellia in assembly language can encrypt on a Pentium III (1.13 GHz) at the rate of 471 Mbits per second. In addition, a distinguishing feature is its small hardware design. A hardware implementation, which includes encryption, decryption, and the key schedule for 128-bit keys, occupies only 9.66 K gates using a 0.35 µm CMOS ASIC library. This is in the smallest class among all existing 128-bit block ciphers. It perfectly meets the current market requirements in wireless cards, for instance, where low power consumption is essential.
ER -