The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
L'article décrit la méthode de pliage des fonctions logiques pour réduire la taille des mémoires afin de conserver les fonctions. Le repliement est basé sur la relation de fractions de fonctions logiques. Si la fonction logique comprend 2 ou 3 parties identiques, alors une seule partie doit être conservée et les autres parties peuvent être omises. Nous montrons que la fonction logique d’addition de 1 bit peut être réduite de moitié en utilisant la relation NON au niveau du bit et la relation OU au niveau du bit. Le document présente également 3-1 LUT avec le mécanisme de pliage. Un additionneur complet peut être implémenté en utilisant une seule LUT 3-1 avec le pliage. Les opérations ET et OU multibits peuvent être mappées sur nos LUT sans utiliser le circuit en cascade supplémentaire mais en utilisant le circuit de report pour l'addition. Nous avons également testé la capacité de mappage de 4 fonctions d'entrée sur nos 3-1 LUT avec des mécanismes de repliement et de propagation de report. Nous avons montré la réduction de la consommation de surface lors de l'utilisation de nos LUT par rapport au cas utilisant des LUT 4-1 sur plusieurs circuits de référence.
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Shinji KIMURA, Atsushi ISHII, Takashi HORIYAMA, Masaki NAKANISHI, Hirotsugu KAJIHARA, Katsumasa WATANABE, "Look Up Table Compaction Based on Folding of Logic Functions" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 12, pp. 2701-2707, December 2002, doi: .
Abstract: The paper describes the folding method of logic functions to reduce the size of memories to keep the functions. The folding is based on the relation of fractions of logic functions. If the logic function includes 2 or 3 same parts, then only one part should be kept and other parts can be omitted. We show that the logic function of 1-bit addition can be reduced to half size using the bit-wise NOT relation and the bit-wise OR relation. The paper also introduces 3-1 LUT's with the folding mechanism. A full adder can be implemented using only one 3-1 LUT with the folding. Multi-bit AND and OR operations can be mapped to our LUT's not using the extra cascading circuit but using the carry circuit for addition. We have also tested the mapping capability of 4 input functions to our 3-1 LUT's with folding and carry propagation mechanisms. We have shown the reduction of the area consumption when using our LUT's compared to the case using 4-1 LUT's on several benchmark circuits.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_12_2701/_p
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@ARTICLE{e85-a_12_2701,
author={Shinji KIMURA, Atsushi ISHII, Takashi HORIYAMA, Masaki NAKANISHI, Hirotsugu KAJIHARA, Katsumasa WATANABE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Look Up Table Compaction Based on Folding of Logic Functions},
year={2002},
volume={E85-A},
number={12},
pages={2701-2707},
abstract={The paper describes the folding method of logic functions to reduce the size of memories to keep the functions. The folding is based on the relation of fractions of logic functions. If the logic function includes 2 or 3 same parts, then only one part should be kept and other parts can be omitted. We show that the logic function of 1-bit addition can be reduced to half size using the bit-wise NOT relation and the bit-wise OR relation. The paper also introduces 3-1 LUT's with the folding mechanism. A full adder can be implemented using only one 3-1 LUT with the folding. Multi-bit AND and OR operations can be mapped to our LUT's not using the extra cascading circuit but using the carry circuit for addition. We have also tested the mapping capability of 4 input functions to our 3-1 LUT's with folding and carry propagation mechanisms. We have shown the reduction of the area consumption when using our LUT's compared to the case using 4-1 LUT's on several benchmark circuits.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - Look Up Table Compaction Based on Folding of Logic Functions
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2701
EP - 2707
AU - Shinji KIMURA
AU - Atsushi ISHII
AU - Takashi HORIYAMA
AU - Masaki NAKANISHI
AU - Hirotsugu KAJIHARA
AU - Katsumasa WATANABE
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2002
AB - The paper describes the folding method of logic functions to reduce the size of memories to keep the functions. The folding is based on the relation of fractions of logic functions. If the logic function includes 2 or 3 same parts, then only one part should be kept and other parts can be omitted. We show that the logic function of 1-bit addition can be reduced to half size using the bit-wise NOT relation and the bit-wise OR relation. The paper also introduces 3-1 LUT's with the folding mechanism. A full adder can be implemented using only one 3-1 LUT with the folding. Multi-bit AND and OR operations can be mapped to our LUT's not using the extra cascading circuit but using the carry circuit for addition. We have also tested the mapping capability of 4 input functions to our 3-1 LUT's with folding and carry propagation mechanisms. We have shown the reduction of the area consumption when using our LUT's compared to the case using 4-1 LUT's on several benchmark circuits.
ER -