The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cette lettre présente une méthode qui tente de minimiser le nombre de codes de déversement pour résoudre les conflits d'utilisation des registres distribués dans les DSP spécifiques à une application. Il recherche un ensemble de restrictions d'ordre parmi les opérations qui séquentiellent autant que possible les durées de vie des valeurs résidant dans le même registre. Les résultats expérimentaux montrent que la méthode d'analyse proposée réduit le nombre de déversements de registres à 28 %.
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Tatsuo WATANABE, Nagisa ISHIURA, "Register Constraint Analysis to Minimize Spill Code for Application Specific DSPs" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 6, pp. 1541-1544, June 2001, doi: .
Abstract: This letter presents a method which attempts to minimize the number of spill codes to resolve usage conflicts of distributed registers in application specific DSPs. It searches for a set of ordering restrictions among operations which sequentialize the lifetimes of the values residing in the same register as much as possible. Experimental results show that the proposed analysis method reduces the number of register spills into 28%.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_6_1541/_p
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@ARTICLE{e84-a_6_1541,
author={Tatsuo WATANABE, Nagisa ISHIURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Register Constraint Analysis to Minimize Spill Code for Application Specific DSPs},
year={2001},
volume={E84-A},
number={6},
pages={1541-1544},
abstract={This letter presents a method which attempts to minimize the number of spill codes to resolve usage conflicts of distributed registers in application specific DSPs. It searches for a set of ordering restrictions among operations which sequentialize the lifetimes of the values residing in the same register as much as possible. Experimental results show that the proposed analysis method reduces the number of register spills into 28%.},
keywords={},
doi={},
ISSN={},
month={June},}
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TY - JOUR
TI - Register Constraint Analysis to Minimize Spill Code for Application Specific DSPs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1541
EP - 1544
AU - Tatsuo WATANABE
AU - Nagisa ISHIURA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2001
AB - This letter presents a method which attempts to minimize the number of spill codes to resolve usage conflicts of distributed registers in application specific DSPs. It searches for a set of ordering restrictions among operations which sequentialize the lifetimes of the values residing in the same register as much as possible. Experimental results show that the proposed analysis method reduces the number of register spills into 28%.
ER -