The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dans cet article, nous proposons une approche de génération de modèles de test pour les circuits de contrôle asynchrones indépendants de la vitesse (SI). Des modèles de test sont générés sur la base d'une séquence spécifiée, qui est dérivée de la spécification d'un circuit cible sous la forme d'un graphique de transition de signal (STG). Puisque la séquence représente le comportement d’un circuit uniquement avec des états stables, l’espace d’état du circuit peut être représenté comme un espace réduit. Une machine à produits, composée d'un circuit sans défaut et d'un circuit défectueux, est construite, puis la séquence spécifiée est appliquée séquentiellement à la machine à produits. Un défaut est détecté lorsque la machine produit produit une incohérence, c'est-à-dire que les valeurs de sortie d'un circuit sans défaut et d'un circuit défectueux sont différentes, et la partie appliquée séquentiellement de la séquence devient un modèle de test pour détecter le défaut. Nous proposons également une méthode de génération de tests utilisant une identification de défaut indétectable ainsi que la séquence spécifiée. Étant donné que l'espace d'état réduit est un sous-ensemble de celui d'une implémentation au niveau de la porte, les modèles de test basés sur une spécification ne peuvent pas détecter certaines erreurs. La méthode proposée identifie à l'avance ces défauts avec une topologie de circuit. BDD est utilisé pour implémenter efficacement les méthodes proposées, car les méthodes proposées comportent de nombreux ensembles d'états et d'opérations d'ensemble. Les résultats expérimentaux montrent que la génération de tests utilisant une spécification permet d'obtenir une couverture élevée des défauts sur un seul modèle de défaut bloqué pour plusieurs circuits SI synthétisés. La génération de tests proposée utilisant une topologie de circuit ainsi qu'une spécification réduit le temps d'exécution pour la génération de tests avec un coût négligeable tout en conservant une couverture élevée des défauts.
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Eunjung OH, Jeong-Gun LEE, Dong-Ik LEE, Ho-Yong CHOI, "Test Generation for SI Asynchronous Circuits with Undetectable Faults from Signal Transition Graph Specification" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 6, pp. 1506-1514, June 2001, doi: .
Abstract: In this paper, we propose an approach to test pattern generation for Speed-Independent (SI) asynchronous control circuits. Test patterns are generated based on a specified sequence, which is derived from the specification of a target circuit in the form of a Signal Transition Graph (STG). Since the sequence represents the behavior of a circuit only with stable states, the state space of the circuit can be represented as reduced one. A product machine, which consists of a fault-free circuit and a faulty circuit, is constructed and then the specified sequence is applied sequentially to the product machine. A fault is detected when the product machine produces inconsistency, i.e., output values of a fault-free circuit and a faulty circuit are different, and the sequentially applied part of the sequence becomes a test pattern to detect the fault. We also propose a test generation method using an undetectable fault identification as well as the specified sequence. Since the reduced state space is a subset of that of a gate level implementation, test patterns based on a specification cannot detect some faults. The proposed method identifies those faults with a circuit topology in advance. BDD is used to implement the proposed methods efficiently, since the proposed methods have a lot of state sets and set operations. Experimental results show that the test generation using a specification achieves high fault coverage over single stuck-at fault model for several synthesized SI circuits. The proposed test generation using a circuit topology as well as a specification decreases execution time for test generation with negligible cost retaining high fault coverage.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_6_1506/_p
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@ARTICLE{e84-a_6_1506,
author={Eunjung OH, Jeong-Gun LEE, Dong-Ik LEE, Ho-Yong CHOI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Test Generation for SI Asynchronous Circuits with Undetectable Faults from Signal Transition Graph Specification},
year={2001},
volume={E84-A},
number={6},
pages={1506-1514},
abstract={In this paper, we propose an approach to test pattern generation for Speed-Independent (SI) asynchronous control circuits. Test patterns are generated based on a specified sequence, which is derived from the specification of a target circuit in the form of a Signal Transition Graph (STG). Since the sequence represents the behavior of a circuit only with stable states, the state space of the circuit can be represented as reduced one. A product machine, which consists of a fault-free circuit and a faulty circuit, is constructed and then the specified sequence is applied sequentially to the product machine. A fault is detected when the product machine produces inconsistency, i.e., output values of a fault-free circuit and a faulty circuit are different, and the sequentially applied part of the sequence becomes a test pattern to detect the fault. We also propose a test generation method using an undetectable fault identification as well as the specified sequence. Since the reduced state space is a subset of that of a gate level implementation, test patterns based on a specification cannot detect some faults. The proposed method identifies those faults with a circuit topology in advance. BDD is used to implement the proposed methods efficiently, since the proposed methods have a lot of state sets and set operations. Experimental results show that the test generation using a specification achieves high fault coverage over single stuck-at fault model for several synthesized SI circuits. The proposed test generation using a circuit topology as well as a specification decreases execution time for test generation with negligible cost retaining high fault coverage.},
keywords={},
doi={},
ISSN={},
month={June},}
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TY - JOUR
TI - Test Generation for SI Asynchronous Circuits with Undetectable Faults from Signal Transition Graph Specification
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1506
EP - 1514
AU - Eunjung OH
AU - Jeong-Gun LEE
AU - Dong-Ik LEE
AU - Ho-Yong CHOI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2001
AB - In this paper, we propose an approach to test pattern generation for Speed-Independent (SI) asynchronous control circuits. Test patterns are generated based on a specified sequence, which is derived from the specification of a target circuit in the form of a Signal Transition Graph (STG). Since the sequence represents the behavior of a circuit only with stable states, the state space of the circuit can be represented as reduced one. A product machine, which consists of a fault-free circuit and a faulty circuit, is constructed and then the specified sequence is applied sequentially to the product machine. A fault is detected when the product machine produces inconsistency, i.e., output values of a fault-free circuit and a faulty circuit are different, and the sequentially applied part of the sequence becomes a test pattern to detect the fault. We also propose a test generation method using an undetectable fault identification as well as the specified sequence. Since the reduced state space is a subset of that of a gate level implementation, test patterns based on a specification cannot detect some faults. The proposed method identifies those faults with a circuit topology in advance. BDD is used to implement the proposed methods efficiently, since the proposed methods have a lot of state sets and set operations. Experimental results show that the test generation using a specification achieves high fault coverage over single stuck-at fault model for several synthesized SI circuits. The proposed test generation using a circuit topology as well as a specification decreases execution time for test generation with negligible cost retaining high fault coverage.
ER -