The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article propose un algorithme d'optimisation zone/temps dans un système de synthèse de haut niveau pour les matériels basés sur le contrôle. Étant donné un graphe d'appel dont le nœud correspond à un flux de contrôle d'un programme d'application, l'algorithme génère un ensemble de graphes de transition d'état qui représente le graphe d'appel d'entrée sous contrainte de zone et de timing. Dans l'algorithme, d'abord des graphiques de transition d'état qui satisfont uniquement à la contrainte de temps sont générés et ensuite ils sont transformés afin qu'ils puissent satisfaire la contrainte de zone. Étant donné que l'algorithme est directement appliqué aux graphiques de flux de contrôle, il peut traiter des flux de contrôle tels que des processus bit à bit et des branches conditionnelles. En outre, l'algorithme synthétise plusieurs architectures matérielles candidates à partir d'un seul graphe d'appel pour un programme d'application. Les concepteurs d'un programme d'application peuvent sélectionner plusieurs bonnes architectures matérielles parmi les candidats en fonction de plusieurs critères de conception. Les résultats expérimentaux pour plusieurs matériels basés sur le contrôle démontrent l'efficacité et l'efficience de l'algorithme.
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Nozomu TOGAWA, Masayuki IENAGA, Masao YANAGISAWA, Tatsuo OHTSUKI, "An Area/Time Optimizing Algorithm in High-Level Synthesis of Control-Based Hardwares" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 5, pp. 1166-1176, May 2001, doi: .
Abstract: This paper proposes an area/time optimizing algorithm in a high-level synthesis system for control-based hardwares. Given a call graph whose node corresponds to a control flow of an application program, the algorithm generates a set of state-transition graphs which represents the input call graph under area and timing constraint. In the algorithm, first state-transition graphs which satisfy only timing constraint are generated and second they are transformed so that they can satisfy area constraint. Since the algorithm is directly applied to control-flow graphs, it can deal with control flows such as bit-wise processes and conditional branches. Further, the algorithm synthesizes more than one hardware architecture candidates from a single call graph for an application program. Designers of an application program can select several good hardware architectures among candidates depending on multiple design criteria. Experimental results for several control-based hardwares demonstrate effectiveness and efficiency of the algorithm.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_5_1166/_p
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@ARTICLE{e84-a_5_1166,
author={Nozomu TOGAWA, Masayuki IENAGA, Masao YANAGISAWA, Tatsuo OHTSUKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Area/Time Optimizing Algorithm in High-Level Synthesis of Control-Based Hardwares},
year={2001},
volume={E84-A},
number={5},
pages={1166-1176},
abstract={This paper proposes an area/time optimizing algorithm in a high-level synthesis system for control-based hardwares. Given a call graph whose node corresponds to a control flow of an application program, the algorithm generates a set of state-transition graphs which represents the input call graph under area and timing constraint. In the algorithm, first state-transition graphs which satisfy only timing constraint are generated and second they are transformed so that they can satisfy area constraint. Since the algorithm is directly applied to control-flow graphs, it can deal with control flows such as bit-wise processes and conditional branches. Further, the algorithm synthesizes more than one hardware architecture candidates from a single call graph for an application program. Designers of an application program can select several good hardware architectures among candidates depending on multiple design criteria. Experimental results for several control-based hardwares demonstrate effectiveness and efficiency of the algorithm.},
keywords={},
doi={},
ISSN={},
month={May},}
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TY - JOUR
TI - An Area/Time Optimizing Algorithm in High-Level Synthesis of Control-Based Hardwares
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1166
EP - 1176
AU - Nozomu TOGAWA
AU - Masayuki IENAGA
AU - Masao YANAGISAWA
AU - Tatsuo OHTSUKI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 5
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - May 2001
AB - This paper proposes an area/time optimizing algorithm in a high-level synthesis system for control-based hardwares. Given a call graph whose node corresponds to a control flow of an application program, the algorithm generates a set of state-transition graphs which represents the input call graph under area and timing constraint. In the algorithm, first state-transition graphs which satisfy only timing constraint are generated and second they are transformed so that they can satisfy area constraint. Since the algorithm is directly applied to control-flow graphs, it can deal with control flows such as bit-wise processes and conditional branches. Further, the algorithm synthesizes more than one hardware architecture candidates from a single call graph for an application program. Designers of an application program can select several good hardware architectures among candidates depending on multiple design criteria. Experimental results for several control-based hardwares demonstrate effectiveness and efficiency of the algorithm.
ER -