The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
L'implémentation matérielle d'un code de nœud de tore discret de haute dimension proposé a été réalisée avec succès sur une puce ASIC. Le code a été élaboré pendant plus d'une décennie à l'Université préfectorale d'Aichi et aux instituts de technologie de Nagoya, tous deux situés à Nagoya, au Japon. Le fonctionnement du matériel a montré la capacité de corriger les erreurs environ cinq à dix fois plus longues que les codes conventionnels, comme prévu par la configuration et la théorie du code. Le résultat en matière de correction d'erreurs aléatoires était également excellent, en particulier pour une plage de taux d'erreur gravement dégradée allant du centième au dixième, ainsi que pour des caractéristiques de qualité supérieure dépassant 10.-6. L'opération était assez stable au pire taux d'erreur binaire et atteignait une vitesse élevée allant jusqu'à 50 Mbps, puisque la configuration codeur-décodeur consistait simplement en un assemblage de code de contrôle de parité et de circuits matériels sans chemin de boucle critique. L'architecture matérielle a une configuration unique et convient à la conception d'ASIC à grande échelle. Le code développé peut être utilisé pour des applications plus larges telles que l'informatique mobile et les communications numériques qualifiées, car il devrait fonctionner correctement dans des situations de canaux dégradés et de haute qualité.
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Yuuichi HAMASUNA, Masanori YAMAMURA, Toshio ISHIZAKA, Masaaki MATSUO, Masayasu HATA, Ichi TAKUMI, "Hardware Implementation of the High-Dimensional Discrete Torus Knot Code" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 4, pp. 949-956, April 2001, doi: .
Abstract: The hardware implementation of a proposed high dimensional discrete torus knot code was successfully realized on an ASIC chip. The code has been worked on for more than a decade since then at Aichi Prefectural University and Nagoya Institutes of Technology, both in Nagoya, Japan. The hardware operation showed the ability to correct the errors about five to ten times the burst length, compared to the conventional codes, as expected from the code configuration and theory. The result in random error correction was also excellent, especially at a severely degraded error rate range of one hundredth to one tenth, and also for high grade characteristic exceeding 10-6. The operation was quite stable at the worst bit error rate and realized a high speed up to 50 Mbps, since the coder-decoder configuration consisted merely of an assemblage of parity check code and hardware circuitry with no critical loop path. The hardware architecture has a unique configuration and is suitable for large scale ASIC design. The developed code can be utilized for wider applications such as mobile computing and qualified digital communications, since the code will be expected to work well in both degraded and high grade channel situations.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_4_949/_p
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@ARTICLE{e84-a_4_949,
author={Yuuichi HAMASUNA, Masanori YAMAMURA, Toshio ISHIZAKA, Masaaki MATSUO, Masayasu HATA, Ichi TAKUMI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Hardware Implementation of the High-Dimensional Discrete Torus Knot Code},
year={2001},
volume={E84-A},
number={4},
pages={949-956},
abstract={The hardware implementation of a proposed high dimensional discrete torus knot code was successfully realized on an ASIC chip. The code has been worked on for more than a decade since then at Aichi Prefectural University and Nagoya Institutes of Technology, both in Nagoya, Japan. The hardware operation showed the ability to correct the errors about five to ten times the burst length, compared to the conventional codes, as expected from the code configuration and theory. The result in random error correction was also excellent, especially at a severely degraded error rate range of one hundredth to one tenth, and also for high grade characteristic exceeding 10-6. The operation was quite stable at the worst bit error rate and realized a high speed up to 50 Mbps, since the coder-decoder configuration consisted merely of an assemblage of parity check code and hardware circuitry with no critical loop path. The hardware architecture has a unique configuration and is suitable for large scale ASIC design. The developed code can be utilized for wider applications such as mobile computing and qualified digital communications, since the code will be expected to work well in both degraded and high grade channel situations.},
keywords={},
doi={},
ISSN={},
month={April},}
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TY - JOUR
TI - Hardware Implementation of the High-Dimensional Discrete Torus Knot Code
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 949
EP - 956
AU - Yuuichi HAMASUNA
AU - Masanori YAMAMURA
AU - Toshio ISHIZAKA
AU - Masaaki MATSUO
AU - Masayasu HATA
AU - Ichi TAKUMI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2001
AB - The hardware implementation of a proposed high dimensional discrete torus knot code was successfully realized on an ASIC chip. The code has been worked on for more than a decade since then at Aichi Prefectural University and Nagoya Institutes of Technology, both in Nagoya, Japan. The hardware operation showed the ability to correct the errors about five to ten times the burst length, compared to the conventional codes, as expected from the code configuration and theory. The result in random error correction was also excellent, especially at a severely degraded error rate range of one hundredth to one tenth, and also for high grade characteristic exceeding 10-6. The operation was quite stable at the worst bit error rate and realized a high speed up to 50 Mbps, since the coder-decoder configuration consisted merely of an assemblage of parity check code and hardware circuitry with no critical loop path. The hardware architecture has a unique configuration and is suitable for large scale ASIC design. The developed code can be utilized for wider applications such as mobile computing and qualified digital communications, since the code will be expected to work well in both degraded and high grade channel situations.
ER -