The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Une approche au niveau système pour une réduction de la puissance de la mémoire est proposée dans cet article. L'idée de base consiste à allouer des codes objets fréquemment exécutés dans une petite mémoire de sous-programme et à optimiser la tension d'alimentation et la tension de seuil de la mémoire de sous-programme. Étant donné que la mémoire à grande échelle contient de nombreux chemins directs depuis l'alimentation vers la terre, la dissipation de puissance provoquée par un courant de fuite inférieur au seuil est plus grave que la dissipation de puissance dynamique. Notre approche optimise la taille de la mémoire du sous-programme, la tension d'alimentation et la tension de seuil afin de minimiser la dissipation de puissance de la mémoire, y compris la dissipation de puissance statique provoquée par le courant de fuite. Un algorithme heuristique qui détermine simultanément l'allocation de code, la tension d'alimentation et la tension de seuil afin de minimiser la dissipation de puissance des mémoires est également proposé. Nos expériences avec certains programmes de référence démontrent des réductions d'énergie significatives jusqu'à 80% par rapport à une mémoire de programme qui n'utilise pas notre approche.
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Tohru ISHIHARA, Kunihiro ASADA, "A System Level Optimization Technique for Application Specific Low Power Memories" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2755-2761, November 2001, doi: .
Abstract: A system level approach for a memory power reduction is proposed in this paper. The basic idea is allocating frequently executed object codes into a small subprogram memory and optimizing supply voltage and threshold voltage of the subprogram memory. Since large scale memory contains a lot of direct paths from power supply to ground, power dissipation caused by subthreshold leakage current is more serious than dynamic power dissipation. Our approach optimizes the size of subprogram memory, supply voltage, and threshold voltage so as to minimize memory power dissipation including static power dissipation caused by leakage current. A heuristic algorithm which determines code allocation, supply voltage, and threshold voltage simultaneously so as to minimize power dissipation of memories is proposed as well. Our experiments with some benchmark programs demonstrate significant energy reductions up to 80% over a program memory which does not employ our approach.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2755/_p
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@ARTICLE{e84-a_11_2755,
author={Tohru ISHIHARA, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A System Level Optimization Technique for Application Specific Low Power Memories},
year={2001},
volume={E84-A},
number={11},
pages={2755-2761},
abstract={A system level approach for a memory power reduction is proposed in this paper. The basic idea is allocating frequently executed object codes into a small subprogram memory and optimizing supply voltage and threshold voltage of the subprogram memory. Since large scale memory contains a lot of direct paths from power supply to ground, power dissipation caused by subthreshold leakage current is more serious than dynamic power dissipation. Our approach optimizes the size of subprogram memory, supply voltage, and threshold voltage so as to minimize memory power dissipation including static power dissipation caused by leakage current. A heuristic algorithm which determines code allocation, supply voltage, and threshold voltage simultaneously so as to minimize power dissipation of memories is proposed as well. Our experiments with some benchmark programs demonstrate significant energy reductions up to 80% over a program memory which does not employ our approach.},
keywords={},
doi={},
ISSN={},
month={November},}
Copier
TY - JOUR
TI - A System Level Optimization Technique for Application Specific Low Power Memories
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2755
EP - 2761
AU - Tohru ISHIHARA
AU - Kunihiro ASADA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - A system level approach for a memory power reduction is proposed in this paper. The basic idea is allocating frequently executed object codes into a small subprogram memory and optimizing supply voltage and threshold voltage of the subprogram memory. Since large scale memory contains a lot of direct paths from power supply to ground, power dissipation caused by subthreshold leakage current is more serious than dynamic power dissipation. Our approach optimizes the size of subprogram memory, supply voltage, and threshold voltage so as to minimize memory power dissipation including static power dissipation caused by leakage current. A heuristic algorithm which determines code allocation, supply voltage, and threshold voltage simultaneously so as to minimize power dissipation of memories is proposed as well. Our experiments with some benchmark programs demonstrate significant energy reductions up to 80% over a program memory which does not employ our approach.
ER -