The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Des décalages cycliques sont nécessaires dans de nombreuses parties centrales des microprocesseurs, des unités à virgule flottante et des DSP. La principale difficulté des conceptions de leviers de vitesses cycliques classiques réside dans les longues connexions filaires internes. Pour cette raison, nous proposons des configurations de décalage cyclique qui améliorent la longueur de fil accumulée sur le chemin critique en réorganisant l'emplacement des portes logiques. Nous pouvons montrer que de cette manière, la complexité de la longueur du fil sur le chemin critique peut être réduite de Ω(n enregistrer (n)) dans les conceptions conventionnelles pour O(n) dans nos conceptions optimisées où n est la largeur de l'opérande décalé. Pour le cas pratique de n=64, nous raccourcissons la longueur de fil accumulée sur le chemin critique d'un facteur 2.20. Dans la même conception, la taille maximale d'un filet qui doit être actionné par une seule porte est réduite d'un facteur 1.86. Cela conduit à des conceptions de leviers de vitesses cycliques plus rapides avec une dissipation de puissance plus faible.
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Peter-Michael SEIDEL, Mark A. HILLEBRAND, Thomas SCHURGER, "Reducing Wire Lengths in the Layout of Cyclic Shifters" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2714-2721, November 2001, doi: .
Abstract: Cyclic shifters are required in many central parts of microprocessors, floating-point units and DSPs. The main difficulty in conventional cyclic shifter designs are the long internal wire connections. For this reason we propose cyclic shifter layouts that improve the accumulated wire length on the critical path by rearranging the placement of the logical gates. We can show that in this way the wire length complexity on the critical path can be reduced from Ω(n log (n)) in conventional designs to O(n) in our optimized designs where n is the width of the shifted operand. For the practical case of n=64 we shorten the accumulated wire length on the critical path by a factor of 2.20. In the same design the maximal size of a net that has to be driven by a single gate is cut down by a factor of 1.86. This leads to faster cyclic shifter designs with lower power dissipation.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2714/_p
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@ARTICLE{e84-a_11_2714,
author={Peter-Michael SEIDEL, Mark A. HILLEBRAND, Thomas SCHURGER, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Reducing Wire Lengths in the Layout of Cyclic Shifters},
year={2001},
volume={E84-A},
number={11},
pages={2714-2721},
abstract={Cyclic shifters are required in many central parts of microprocessors, floating-point units and DSPs. The main difficulty in conventional cyclic shifter designs are the long internal wire connections. For this reason we propose cyclic shifter layouts that improve the accumulated wire length on the critical path by rearranging the placement of the logical gates. We can show that in this way the wire length complexity on the critical path can be reduced from Ω(n log (n)) in conventional designs to O(n) in our optimized designs where n is the width of the shifted operand. For the practical case of n=64 we shorten the accumulated wire length on the critical path by a factor of 2.20. In the same design the maximal size of a net that has to be driven by a single gate is cut down by a factor of 1.86. This leads to faster cyclic shifter designs with lower power dissipation.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - Reducing Wire Lengths in the Layout of Cyclic Shifters
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2714
EP - 2721
AU - Peter-Michael SEIDEL
AU - Mark A. HILLEBRAND
AU - Thomas SCHURGER
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - Cyclic shifters are required in many central parts of microprocessors, floating-point units and DSPs. The main difficulty in conventional cyclic shifter designs are the long internal wire connections. For this reason we propose cyclic shifter layouts that improve the accumulated wire length on the critical path by rearranging the placement of the logical gates. We can show that in this way the wire length complexity on the critical path can be reduced from Ω(n log (n)) in conventional designs to O(n) in our optimized designs where n is the width of the shifted operand. For the practical case of n=64 we shorten the accumulated wire length on the critical path by a factor of 2.20. In the same design the maximal size of a net that has to be driven by a single gate is cut down by a factor of 1.86. This leads to faster cyclic shifter designs with lower power dissipation.
ER -