The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Le partitionnement matériel/logiciel est l’un des processus clés d’un système de cosynthèse matériel/logiciel pour les cœurs de processeurs de signaux numériques. Dans le partitionnement matériel/logiciel, l'estimation de la surface et du délai d'un cœur de processeur joue un rôle important puisque le processus de partitionnement matériel/logiciel doit déterminer quelle partie d'un cœur de processeur doit être réalisée par des unités matérielles et quelle partie doit être réalisée par une séquence d'instructions. basé sur le temps d'exécution d'un programme d'application d'entrée et la zone d'un cœur de processeur synthétisé. Cet article propose des équations d'estimation de surface et de retard pour les cœurs de processeurs de signaux numériques. Pour l'estimation de la superficie, nous montrons que la superficie totale d'un cœur de processeur peut être dérivée de la somme de la superficie d'un noyau de processeur et de la superficie des unités matérielles supplémentaires. La zone pour un noyau de processeur peut être principalement obtenue par la zone minimale pour un noyau de processeur et les frais généraux liés à l'ajout d'unités matérielles et de registres. La surface d'une unité matérielle peut être principalement obtenue par son type et sa largeur de bits de fonctionnement. Pour l'estimation du délai, nous montrons que le délai du chemin critique pour un cœur de processeur peut être dérivé du retard d'une unité matérielle qui se trouve sur le chemin critique dans le cœur du processeur. Les résultats expérimentaux démontrent que les erreurs d'estimation de surface sont inférieures à 2 % et les erreurs d'estimation de retard sont inférieures à 2 ns lorsque l'on compare la surface et le retard estimés avec la surface et le retard synthétisés logiquement.
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Nozomu TOGAWA, Yoshiharu KATAOKA, Yuichiro MIYAOKA, Masao YANAGISAWA, Tatsuo OHTSUKI, "Area and Delay Estimation in Hardware/Software Cosynthesis for Digital Signal Processor Cores" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2639-2647, November 2001, doi: .
Abstract: Hardware/software partitioning is one of the key processes in a hardware/software cosynthesis system for digital signal processor cores. In hardware/software partitioning, area and delay estimation of a processor core plays an important role since the hardware/software partitioning process must determine which part of a processor core should be realized by hardware units and which part should be realized by a sequence of instructions based on execution time of an input application program and area of a synthesized processor core. This paper proposes area and delay estimation equations for digital signal processor cores. For area estimation, we show that total area for a processor core can be derived from the sum of area for a processor kernel and area for additional hardware units. Area for a processor kernel can be mainly obtained by minimum area for a processor kernel and overheads for adding hardware units and registers. Area for a hardware unit can be mainly obtained by its type and operation bit width. For delay estimation, we show that critical path delay for a processor core can be derived from the delay of a hardware unit which is on the critical path in the processor core. Experimental results demonstrate that errors of area estimation are less than 2% and errors of delay estimation are less than 2 ns when comparing estimated area and delay with logic-synthesized area and delay.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2639/_p
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@ARTICLE{e84-a_11_2639,
author={Nozomu TOGAWA, Yoshiharu KATAOKA, Yuichiro MIYAOKA, Masao YANAGISAWA, Tatsuo OHTSUKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Area and Delay Estimation in Hardware/Software Cosynthesis for Digital Signal Processor Cores},
year={2001},
volume={E84-A},
number={11},
pages={2639-2647},
abstract={Hardware/software partitioning is one of the key processes in a hardware/software cosynthesis system for digital signal processor cores. In hardware/software partitioning, area and delay estimation of a processor core plays an important role since the hardware/software partitioning process must determine which part of a processor core should be realized by hardware units and which part should be realized by a sequence of instructions based on execution time of an input application program and area of a synthesized processor core. This paper proposes area and delay estimation equations for digital signal processor cores. For area estimation, we show that total area for a processor core can be derived from the sum of area for a processor kernel and area for additional hardware units. Area for a processor kernel can be mainly obtained by minimum area for a processor kernel and overheads for adding hardware units and registers. Area for a hardware unit can be mainly obtained by its type and operation bit width. For delay estimation, we show that critical path delay for a processor core can be derived from the delay of a hardware unit which is on the critical path in the processor core. Experimental results demonstrate that errors of area estimation are less than 2% and errors of delay estimation are less than 2 ns when comparing estimated area and delay with logic-synthesized area and delay.},
keywords={},
doi={},
ISSN={},
month={November},}
Copier
TY - JOUR
TI - Area and Delay Estimation in Hardware/Software Cosynthesis for Digital Signal Processor Cores
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2639
EP - 2647
AU - Nozomu TOGAWA
AU - Yoshiharu KATAOKA
AU - Yuichiro MIYAOKA
AU - Masao YANAGISAWA
AU - Tatsuo OHTSUKI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - Hardware/software partitioning is one of the key processes in a hardware/software cosynthesis system for digital signal processor cores. In hardware/software partitioning, area and delay estimation of a processor core plays an important role since the hardware/software partitioning process must determine which part of a processor core should be realized by hardware units and which part should be realized by a sequence of instructions based on execution time of an input application program and area of a synthesized processor core. This paper proposes area and delay estimation equations for digital signal processor cores. For area estimation, we show that total area for a processor core can be derived from the sum of area for a processor kernel and area for additional hardware units. Area for a processor kernel can be mainly obtained by minimum area for a processor kernel and overheads for adding hardware units and registers. Area for a hardware unit can be mainly obtained by its type and operation bit width. For delay estimation, we show that critical path delay for a processor core can be derived from the delay of a hardware unit which is on the critical path in the processor core. Experimental results demonstrate that errors of area estimation are less than 2% and errors of delay estimation are less than 2 ns when comparing estimated area and delay with logic-synthesized area and delay.
ER -