The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Un modulateur sigma-delta de second ordre avec un quantificateur interne de 3 bits doté d'une mise à l'échelle du gain d'un CAN interne et d'un DAC interne très simple a été conçu et implémenté dans un processus CMOS double poly double métal de 0.8 µm. Nous avons amélioré les performances du modulateur grâce à la mise à l'échelle du gain d'un CAN interne 3 bits et à la conception du DAC interne sans erreur en utilisant de simples portes logiques. La spécification de chaque composant est déterminée pour que le modulateur ait une résolution de 14 bits par modélisation basée sur le temps et les composants conçus satisfont aux spécifications requises. Le SNR maximal de 87 dB et la plage dynamique de 87 dB ont été atteints à une fréquence d'horloge de 2.816 MHz pour une bande de base de 22 kHz. Les résultats mesurés montrent que le modulateur fabriqué abaisse le SNR de 14 dB par rapport à celui de la simulation en raison de la source d'entrée non idéale et des facteurs d'erreur ignorés dans la modélisation tels que les condensateurs variables en tension, etc.
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Byung-Woog CHO, Pyung CHOI, Jun-Rim CHOI, Dae-Hyuk KWON, Byung-Ki SOHN, "A Second-Order Sigma-Delta Modulator with a Gain Scaling of ADC and a Simple Multibit DAC" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 6, pp. 1192-1198, June 2000, doi: .
Abstract: A second-order sigma-delta modulator with a 3-bit internal quantizer featuring a gain scaling of an internal ADC and a very simple internal DAC has been designed and implemented in a 0.8 µm double-poly double-metal CMOS process. We improved the performance of the modulator with the gain scaling of a 3-bit internal ADC and design of the internal error-free DAC with using simple logic gates. The specification of each component is determined for the modulator to have 14-bit resolution by time based modeling and the designed components satisfy the required specifications. The peak SNR of 87 dB and dynamic range of 87 dB were achieved at a clock rate of 2.816 MHz for 22 kHz baseband. The measured results show that the fabricated modulator lower SNR by 14 dB than that of the simulation due to the non-ideal input source and the disregarded error factors in the modeling such as the voltage variable capacitors etc.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_6_1192/_p
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@ARTICLE{e83-a_6_1192,
author={Byung-Woog CHO, Pyung CHOI, Jun-Rim CHOI, Dae-Hyuk KWON, Byung-Ki SOHN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Second-Order Sigma-Delta Modulator with a Gain Scaling of ADC and a Simple Multibit DAC},
year={2000},
volume={E83-A},
number={6},
pages={1192-1198},
abstract={A second-order sigma-delta modulator with a 3-bit internal quantizer featuring a gain scaling of an internal ADC and a very simple internal DAC has been designed and implemented in a 0.8 µm double-poly double-metal CMOS process. We improved the performance of the modulator with the gain scaling of a 3-bit internal ADC and design of the internal error-free DAC with using simple logic gates. The specification of each component is determined for the modulator to have 14-bit resolution by time based modeling and the designed components satisfy the required specifications. The peak SNR of 87 dB and dynamic range of 87 dB were achieved at a clock rate of 2.816 MHz for 22 kHz baseband. The measured results show that the fabricated modulator lower SNR by 14 dB than that of the simulation due to the non-ideal input source and the disregarded error factors in the modeling such as the voltage variable capacitors etc.},
keywords={},
doi={},
ISSN={},
month={June},}
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TY - JOUR
TI - A Second-Order Sigma-Delta Modulator with a Gain Scaling of ADC and a Simple Multibit DAC
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1192
EP - 1198
AU - Byung-Woog CHO
AU - Pyung CHOI
AU - Jun-Rim CHOI
AU - Dae-Hyuk KWON
AU - Byung-Ki SOHN
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2000
AB - A second-order sigma-delta modulator with a 3-bit internal quantizer featuring a gain scaling of an internal ADC and a very simple internal DAC has been designed and implemented in a 0.8 µm double-poly double-metal CMOS process. We improved the performance of the modulator with the gain scaling of a 3-bit internal ADC and design of the internal error-free DAC with using simple logic gates. The specification of each component is determined for the modulator to have 14-bit resolution by time based modeling and the designed components satisfy the required specifications. The peak SNR of 87 dB and dynamic range of 87 dB were achieved at a clock rate of 2.816 MHz for 22 kHz baseband. The measured results show that the fabricated modulator lower SNR by 14 dB than that of the simulation due to the non-ideal input source and the disregarded error factors in the modeling such as the voltage variable capacitors etc.
ER -