The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Les techniques de câblage alternatives se sont révélées très utiles pour de nombreux problèmes EDA. Les techniques de recâblage actuellement utilisées sont principalement basées sur l'ATPG. Dans cet article, nous étudions l'approche consistant à appliquer des méthodes de recherche de modèles locaux purement basées sur des graphes pour localiser des fils alternatifs. La méthode recherche des modèles graphiques minimaux contenant des fils alternatifs limités à 2 arêtes distantes du fil cible. Le résultat expérimental montre que ce schéma est très rapide et présente l’avantage de rechercher facilement les fils alternatifs proches vers l’avant et vers l’arrière. Le nombre total de fils alternatifs recherchés est tout à fait comparable (104 %), par rapport à la version RAMBO à recherche directe uniquement, et le temps CPU est 200 fois plus rapide. Nous illustrons également son utilisation, parmi tant d'autres, par un simple couplage avec les opérations algébriques du SIS et laissons cet outil de recâblage servir de moteur perturbateur de netlist pour la minimisation logique. Le schéma de couplage montre une réduction supplémentaire de 8.5 % de la surface par rapport à l'application d'un script algébrique seul, avec une surcharge CPU presque négligeable consacrée au recâblage.
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Yu-Liang WU, Wangning LONG, Hongbing FAN, "A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 6, pp. 1131-1137, June 2000, doi: .
Abstract: Alternative wiring techniques have been shown to be very useful for many EDA problems. The currently used rewiring techniques are mainly ATPG based. In this paper, we study the approach of applying purely graph-based local pattern search methods in locating alternative wires. The method searches minimal graph patterns containing alternative wires that limited to 2 edges distant from the target wire. The experimental result shows that this scheme is very fast and has the advantage of searching both the nearby forward and backward alternative wires easily. The overall number of alternative wires searched is quite comparable (104%), compared to the forward search only RAMBO version, and the CPU time is 200 times faster. We also illustrate its usage, among many others, by a simple coupling with the SIS algebraic operations and let this rewiring tool serve as a netlist-perturbing engine for logic minimization. The coupling scheme shows a further reduction of 8.5% in area compared to applying algebraic script alone, with a nearly negligible CPU overhead spent in rewiring.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_6_1131/_p
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@ARTICLE{e83-a_6_1131,
author={Yu-Liang WU, Wangning LONG, Hongbing FAN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks},
year={2000},
volume={E83-A},
number={6},
pages={1131-1137},
abstract={Alternative wiring techniques have been shown to be very useful for many EDA problems. The currently used rewiring techniques are mainly ATPG based. In this paper, we study the approach of applying purely graph-based local pattern search methods in locating alternative wires. The method searches minimal graph patterns containing alternative wires that limited to 2 edges distant from the target wire. The experimental result shows that this scheme is very fast and has the advantage of searching both the nearby forward and backward alternative wires easily. The overall number of alternative wires searched is quite comparable (104%), compared to the forward search only RAMBO version, and the CPU time is 200 times faster. We also illustrate its usage, among many others, by a simple coupling with the SIS algebraic operations and let this rewiring tool serve as a netlist-perturbing engine for logic minimization. The coupling scheme shows a further reduction of 8.5% in area compared to applying algebraic script alone, with a nearly negligible CPU overhead spent in rewiring.},
keywords={},
doi={},
ISSN={},
month={June},}
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TY - JOUR
TI - A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1131
EP - 1137
AU - Yu-Liang WU
AU - Wangning LONG
AU - Hongbing FAN
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2000
AB - Alternative wiring techniques have been shown to be very useful for many EDA problems. The currently used rewiring techniques are mainly ATPG based. In this paper, we study the approach of applying purely graph-based local pattern search methods in locating alternative wires. The method searches minimal graph patterns containing alternative wires that limited to 2 edges distant from the target wire. The experimental result shows that this scheme is very fast and has the advantage of searching both the nearby forward and backward alternative wires easily. The overall number of alternative wires searched is quite comparable (104%), compared to the forward search only RAMBO version, and the CPU time is 200 times faster. We also illustrate its usage, among many others, by a simple coupling with the SIS algebraic operations and let this rewiring tool serve as a netlist-perturbing engine for logic minimization. The coupling scheme shows a further reduction of 8.5% in area compared to applying algebraic script alone, with a nearly negligible CPU overhead spent in rewiring.
ER -