The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Pour FA (automatisation d'usine) et ATE (équipement de test automatique) dans le domaine industriel, le bus standard est nécessaire pour augmenter les performances du système dans un environnement multiprocesseur. Le bus VME (versa module European Package Format) est adapté au bus standard mais présente les caractéristiques suivantes : petit boîtier et faible densité de carte. En outre, la densité des cartes et des semi-conducteurs est devenue un problème important qui affecte le temps de développement, le coût du projet et les diagnostics sur le terrain. Pour s'adapter à cette tendance, dans cet article, l'auteur a composé la révision C. 1 (IEEE Std. P1014-1987) de l'environnement intégré pour la fonction principale telle que l'arbitrage, l'interruption et l'interface entre VMEbus et plusieurs modules de contrôle. De plus, le contrôleur système VME conçu est implémenté sur un FPGA qui peut être situé même dans l'emplacement 1. Les modules de contrôle et de fonction sont codés avec la méthode de description intermédiaire VHDL, puis ces opérations sont vérifiées par simulation. À la suite de l'expérience, l'auteur a confirmé que le plus important concernant le fonctionnement de la minuterie de bus est que le signal d'erreur de bus doit se produire dans un délai de 56 µs et que les modules de commande et de fonction fonctionnent correctement. Ainsi, la bibliothèque VHDL construite sera capable d'appliquer la conception VMEbus et ASIC basée sur le système.
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Kang Hyeon RHEE, "A Study on the Design of VME System Controller" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 6, pp. 1083-1090, June 2000, doi: .
Abstract: For FA (factory automation) and ATE (automatic test equipment) in the industrial area, the standard bus is required to increase the system performance of multiprocessor environment. VME (versa module european package format) bus is appropriated to the standard bus but has the features that is the small of package and the low density of board. Beside, the density of board and semiconductor have grown to become a significant issues that affect the development time, project cost and field diagnostics. To fit this trend, in this paper, the author composed Revision C. 1 (IEEE Std. P1014-1987) of the integrated environment for the main function such as arbitration, interrupt and interface between VMEbus and several control modules. Also the designed VME system controller is implemented on FPGA that can be located even into Slot 1. The control and function modules are coded with VHDL mid-fixed description method and then those operations are verified by simulation. As a result of experiment, the author confirmed that the most important about the operation of Bus timer that Bus error signal should occur within 56 µs, and both control and function modules have the reciprocal operation correctly. Thus, the constructed VHDL library will be able to apply the system based VMEbus and ASIC design.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_6_1083/_p
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@ARTICLE{e83-a_6_1083,
author={Kang Hyeon RHEE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Study on the Design of VME System Controller},
year={2000},
volume={E83-A},
number={6},
pages={1083-1090},
abstract={For FA (factory automation) and ATE (automatic test equipment) in the industrial area, the standard bus is required to increase the system performance of multiprocessor environment. VME (versa module european package format) bus is appropriated to the standard bus but has the features that is the small of package and the low density of board. Beside, the density of board and semiconductor have grown to become a significant issues that affect the development time, project cost and field diagnostics. To fit this trend, in this paper, the author composed Revision C. 1 (IEEE Std. P1014-1987) of the integrated environment for the main function such as arbitration, interrupt and interface between VMEbus and several control modules. Also the designed VME system controller is implemented on FPGA that can be located even into Slot 1. The control and function modules are coded with VHDL mid-fixed description method and then those operations are verified by simulation. As a result of experiment, the author confirmed that the most important about the operation of Bus timer that Bus error signal should occur within 56 µs, and both control and function modules have the reciprocal operation correctly. Thus, the constructed VHDL library will be able to apply the system based VMEbus and ASIC design.},
keywords={},
doi={},
ISSN={},
month={June},}
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TY - JOUR
TI - A Study on the Design of VME System Controller
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1083
EP - 1090
AU - Kang Hyeon RHEE
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2000
AB - For FA (factory automation) and ATE (automatic test equipment) in the industrial area, the standard bus is required to increase the system performance of multiprocessor environment. VME (versa module european package format) bus is appropriated to the standard bus but has the features that is the small of package and the low density of board. Beside, the density of board and semiconductor have grown to become a significant issues that affect the development time, project cost and field diagnostics. To fit this trend, in this paper, the author composed Revision C. 1 (IEEE Std. P1014-1987) of the integrated environment for the main function such as arbitration, interrupt and interface between VMEbus and several control modules. Also the designed VME system controller is implemented on FPGA that can be located even into Slot 1. The control and function modules are coded with VHDL mid-fixed description method and then those operations are verified by simulation. As a result of experiment, the author confirmed that the most important about the operation of Bus timer that Bus error signal should occur within 56 µs, and both control and function modules have the reciprocal operation correctly. Thus, the constructed VHDL library will be able to apply the system based VMEbus and ASIC design.
ER -